Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Restriction/Election
Claims 12-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 13 April 2026.
Examiner’s Note: Claim 12 recites the limitation: A semiconductor device comprising: a lower circuit pattern on a substrate; an upper wiring over the lower circuit pattern; a gate electrode structure including first, second, third and fourth gate electrodes spaced apart from each other over the upper wiring in a first direction substantially perpendicular to an upper surface of the substrate. Due to this limitation the upper wiring must be between the lower circuit pattern and the electrodes, as seen in Species IV and Fig. 58.
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application KR 10-2022-0158864 filed on 24 Nov, 2022. The foreign application is not in English. The certified copy of the foreign priority application KR 10-2022-0158864 has been received. Filing Dates for the Claims — All Claims Not Entitled to Priority DateTo be entitled to the filing date of the foreign priority application KR 10-2022-0158864 that is not in English, an English translation of the non-English language foreign application and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
35 U.S.C. §103 Rejections
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, and 6-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Pub. 20220310515), hereinafter referred to as Lee, in view of Imai et al. (US Pub 20190267391), hereinafter referred to as Imai.
Regarding claim 1, Lee teaches a semiconductor device comprising: a gate electrode structure including first (Lee, 227g, Fig. 11A para 197, see Fig 11A below) , second (Lee, 227g, and 240g, Fig. 1A para 197, see Fig 11A below), and third gate electrodes (Lee, 240g, Fig. 11A para 197, see Fig 11A below), spaced apart from each other on a substrate (Lee, 204, Fig. 11A, para. 184) in a first direction substantially perpendicular to an upper surface of the substrate, each of the first, second, third and fourth gate electrodes extending in a second direction substantially parallel to the upper surface of the substrate; a first memory channel structure (Lee, 47, Fig. 11A, para. 189) extending through the first, second and third gate electrodes on the substrate; a second memory channel structure (Lee, 296a, Fig. 11A, para. 206) contacting an upper surface of the first memory channel structure, and a first contact plug (Lee, 289m Figs. 11A, 12, para. 200) including a lower portion and an upper portion, wherein the upper portion is on and contacting an upper surface of the lower portion, and wherein the lower portion extends partially through the gate electrode structure, wherein the lower portion of the first contact plug extends through the first, second and third gate electrodes, and is electrically insulated from the first and second gate electrodes, and is electrically connected to the third gate electrode (Lee Fig. 12).
Lee does not teach a fourth gate electrode wherein a second memory channel structure extends through the fourth gate electrode.
However, Imai teaches a memory channel structure which extends through a gate electrode situated above the main body of the stack structure (Imai 254, Fig. 56A, paras. 298-299, 318, Per para. 318 I serves as the drain side select gate electrode for the vertical NAND string as per Claim 9 of the application)
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teaching of Lee and the electrode of Imai to provide higher device density (Imai para. 137).
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Regarding claim 6, modified Lee teaches the semiconductor device of claim 1, further comprising an insulation pattern (Lee, 227, 240, Fig. 12, para. 201) between each of portions of a sidewall of the first contact plug facing the first and second gate electrodes, respectively, and a corresponding one of the first and second gate electrodes.
Regarding claim 7, modified Lee teaches the semiconductor device of claim 1 wherein: the second memory channel structure includes a second channel extending in the first direction, the second channel includes a lower portion having a first width (Lee, 55, Fig. 3A, para. 105, para.189), , a middle portion having a second width (Lee, 96a, Fig. 3A, para 107), and a third portion having a third width (Lee, 98b, Fig. 3A, para. 89), and each of the first and third widths is greater than the second width.
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Regarding claim 8, modified Lee teaches the semiconductor device of claim 1, wherein each of the first to third gate electrodes includes a metal (Lee, paras. 188, and 52, para. 188 states that 227g and 240g are the same materials as 27g and 40g, para. 52 states 27g and 40 may be made of metal) and the fourth gate electrode includes doped polysilicon (Imai, para. 297, states that it may be made of a “heavily doped semiconductor material”, polysilicon is well known in the art).
Regarding claim 9, modified Lee teaches the semiconductor device of claim 1, wherein the first gate electrode serves as a ground selection line (GSL) (Lee, GL1, Fig. 3A, para. 95), the second gate electrode serves as a word line (Lee, GM, Fig. 3A, para. 94), the third gate electrode is a gate induced drain leakage (GIDL) electrode (Lee, UT1, Fig. 17, para. 270), and the fourth gate electrode serves as a string selection line (SSL) (Imai, 254, Fig. 56A, para. 318).
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Regarding claim 10, modified Lee teaches the semiconductor device of claim 1, further comprising second contact plugs (Lee, 289, Fig. 11A para. 202, there are multiple instances of 289), each of the second contact plugs including a lower portion and an upper portion on and contacting the lower portion (Lee, Fig. 11A), wherein the lower portion extends partially through the gate electrode structure (Lee, 289, 223’, 234’ Fig. 12), wherein the lower portion of each of the second contact plugs has a width varying in the first direction (Lee, Fig. 12) , and the upper portion of each of the second contact plugs has a width gradually increasing from a bottom toward a top thereof (Lee, 289, Fig. 12), and wherein the lower portion of each of the second contact plugs extends through the first and second gate electrodes, and is electrically insulated from the first gate electrode (Lee, 227, 240, Fig. 12, para. 201) , and is electrically connected to the second gate electrode (Lee, para. 201) .
Regarding claim 11, modified Lee teaches the semiconductor device of claim 10, wherein the second gate electrode is one of a plurality of second gate electrodes spaced apart from each other in the first direction, wherein the lower portion of each of the second contact plugs extends through the plurality of second gate electrodes (Lee, Fig. 11A), and wherein the lower portion of each of the second contact plugs is electrically connected to an uppermost one of the plurality of second gate electrodes, but is not electrically connected to other ones of the plurality of second gate electrodes (Lee Fig. 11A, shows multiple instances of 289, each electrically connected to the topmost gate electrode it extends through, and electrically insulated from the rest by insulators 227 and 240 (see Fig. 12)).
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lee and Imai as applied to claim 1 above, and further in view of Lim et al. (US Pub. 20220077167), hereinafter referred to as Lim.
Regarding claim 2, modified Lee teaches the semiconductor device of claim 1, but does not teach wherein an upper surface of the lower portion of the first contact plug is substantially coplanar with an upper surface of the first memory channel structure.
However, Lim teaches am memory device wherein an upper surface of the lower portion of the first contact plug (Lim, 82, Fig. 2A, para. 68)is substantially coplanar with an upper surface of the first memory channel structure (Lim, 54m Fig. 3A, para. 82, shows the lower portion of the channel structure ending at the top of layer 90c).
Therefore it would have been obvious to one having ordinary skill in the art to combine the teaching of Lee and Imai with the coplanar first portions of Lim to improve integration density and reliability (Lim, para. 4).
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Regarding claim 3, modified Lee the semiconductor device of claim 1, wherein an upper surface of the upper portion of the first contact plug is substantially coplanar with an upper surface of the second memory channel structure
However, Lim teaches am memory device wherein an upper surface of the upper portion of the first contact plug (Lim, 82, Fig. 2A, para. 68, Fig. 2A shows this ending at the top of 90e) is substantially coplanar with an upper surface of the first memory channel structure (Lim, 85a Fig. 3A, para. 82, Fig. 3A shows this ending at the top of layer 90e).
Therefore it would have been obvious to one having ordinary skill in the art to combine the teaching of Lee and Imai with the coplanar first portions of Lim to improve integration density and reliability (Lim, para. 4).
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Lee and Imai as applied to claim 1 above, and further in view of Hirotani et al. (US Pub. 20170236827), hereinafter referred to as Hirotani.
Regarding claim 4, modified Lee teaches the semiconductor device of claim 1, but does not teach wherein the first contact plug includes protrusion portions on portions of a sidewall of the first contact plug facing the first, second and third gate electrodes, respectively, the protrusion portion protruding in a horizontal direction substantially parallel to the upper surface of the substrate.
However, Hirotani teaches a memory plug wherein the plug includes protrusion portions on portions of a sidewall of the first contact plug facing the first, second and third gate electrodes, respectively, the protrusion portion protruding in a horizontal direction substantially parallel to the upper surface of the substrate (Hirotani, MH, Fig. 2, paras.27-29).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teaching of Lee and Imai with the protrusions of Hirotani in order to improve the retention characteristics of the data (Hirotani, para. 3)
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Regarding claim 5, modified Lee teaches the semiconductor device of claim 4, wherein a width in the horizontal direction of an uppermost one of the protrusion portions of the first contact plug (Lee, 289E, Fig. 12) is greater than a width in the horizontal direction of other ones of the protrusion portions (Hirotani, D1, Fig. 2) of the first contact plug. The illustration shows that 298E of Lee extends wider than the insulation on lower layers, while the protrusions of Hirotani stop at the insulator).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee Imai and Lim.
Regarding claim 17, Lee teaches a semiconductor device comprising: a lower circuit pattern (Lee, 208, Fig. 11A, para. 184) on a substrate (Lee, 204, Fig. 11A, para. 184) including first (Lee. MCA, Fig. 11A, para. 186) and second regions (Lee, SA, Fig. 11A, para. 186); a common source plate (CSP) (Lee, 217, Fig. 11A, paras 183, 81) on the lower circuit pattern; a gate electrode structure including first (Lee, 227g, Fig 11A, para. 188, first electrode is the bottommost instance of 227g), second (Lee, 227g, 240g, Fig. 11A, para 188, second electrode are the rest of the plurality of 227g instances), third (Lee, 240g, Fig. 11A, para 188, third electrodes are the plurality of instances of 240g, except the topmost instance), and fourth (Lee, 240g, Fig. 11A, para 188, fourth electrode is the topmost instance of 240g) gate electrodes spaced apart from each other on the CSP in a first direction substantially perpendicular to an upper surface of the substrate, each of the first, second, third, and fourth gate electrodes extending in a second direction substantially parallel to the upper surface of the substrate;
a first memory channel structure extending through the first to fourth gate electrodes on the CSP on the first region of the substrate (Lee, 47, Fig. 11A, para. 189);
a second memory channel structure contacting an upper surface of the first memory channel structure (Lee, 296a Fig. 11A, para 206);
a support structure (Lee, 61, Fig. 11B, para. 191) on the CSP on the second region of the substrate, the support structure partially extending through the gate electrode structure;
a first contact plug (Lee, 289, Fig. 11A, 12, para. 191) including a lower portion and an upper portion, wherein the upper portion is on and contacting an upper surface of the lower portion, and wherein the lower portion extending partially through the gate electrode structure on the second region of the substrate;
and a second contact plug (Lee, 289, Fig. 11A, 12, para. 191, Fig. 11A displays a plurality of contact plugs) including a lower portion and an upper portion, wherein the upper portion is on and contacting an upper surface of the lower portion, and wherein the lower portion extends partially through the gate electrode structure on the second region of the substrate,
wherein: the lower portion of each of the first and second contact plugs has a width varying in the first direction, and the upper portion of each of the first and second contact plugs has a width gradually increasing from a bottom toward a top thereof, each of the first and second contact plugs contacts one of the first to fourth gate electrodes (Lee, 289E, Fig. 12, para 202).
Lee does not teach a fifth gate electrode spaced apart from each other on the CSP in a first direction substantially perpendicular to an upper surface of the substrate, extending in a second direction substantially parallel to the upper surface of the substrate; second memory channel structure extending through the fifth gate electrode; and upper surfaces of the first memory channel structure, the support structure and the lower portions of the first and second contact plugs are substantially coplanar with each other.
However, Imai teaches a memory channel structure which extends through a gate electrode situated above the main body of the stack structure (Imai 254, Fig. 56A, paras. 298-299, 318, Per para. 318 I serves as the drain side select gate electrode for the vertical NAND string as per Claim 9 of the application this).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teaching of Lee and the electrode of Imai to provide higher device density (Imai para. 137).
Additionally, Lim teaches a memory structure wherein the upper surfaces of the first memory channel structure (Lim 54m, Fig. 3A, para. 82), the support structure (Lim, 54s, Fig. 3B, para. 82) and the lower portions of the first and second contact plugs (Lim, 82, Fig. 2A, para. 68) are substantially coplanar with each other (The upper surfaces are al coplanar with the upper surface of the third capping layer 90c).
Therefore it would have been obvious to one having ordinary skill in the art to combine the teaching of Lee and Imai with the coplanar first portions of Lim to improve integration density and reliability (Lim, para. 4).
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Regarding claim 18, modified Lee teaches the semiconductor device of claim 17, wherein the support structure (Lee, 61, Fig. 1, para. 191) is one of a plurality of support structures spaced apart from each other in the second direction and in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction,
and wherein each of the first and second contact plugs (Lee, 89, Fig. 1, para. 83, 89 are gate contact plugs, and fulfill the same purpose as 289 in Fig. 11A)) is disposed in an area surrounded by ones of the plurality of support structures in a plan view.
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Regarding claim 19, modified Lee teaches the semiconductor device of claim 17, wherein each of the first to fourth gate electrodes includes a metal (Lee, paras. 188, and 52, para. 188 states that 227g and 240g are the same materials as 27g and 40g, para. 52 states 27g and 40 may be made of metal) and the fifth gate electrode includes doped polysilicon (Imai, para. 297, states that it may be made of a “heavily doped semiconductor material”, polysilicon is well known in the art).
Regarding claim 20, modified Lee teaches the semiconductor device of claim 19, wherein the first gate electrode serves as a GSL (Lee, GL1, Fig. 3A, para. 95), each of the second and fourth gate electrodes is a GIDL gate electrode (Lee, LT1, UT1, Fig. 17 para. 270), the third gate electrode serves as a word line (Lee, WL, Fig. 17, para. 271, WL is made up of instance of 227g and 240g, and instances of 240g make up the third gate electrodes), and the fifth gate electrode serves as an SSL (Imai, 254, Fig. 56A, para. 318).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Orimoto et al (US Pub 20190027489) teaches a memory device with support pillars.
Hu (US Pub. 20180026045) teaches a memory device where the memory pillars consist of two portions, and the device is divided into different areas.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:00-4:3.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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