DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-9 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected device, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 10, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Gejo et al. (2023/0223464, hereafter Gejo) in view of Ota et al. (2019/0273134, hereafter Ota).
Regarding claim 10, Gejo discloses a semiconductor device, comprising: a first electrode (20, par. 0012); a first semiconductor region (10) located on the first electrode, the first semiconductor region being of a first conductivity type (par. 0012); a second semiconductor region (13) located on a portion of the first semiconductor region, the second semiconductor region being of a second conductivity type (par. 0015); a third semiconductor region (17) located between a portion of the first electrode and the portion of the first semiconductor region, the third semiconductor region being of the second conductivity type (par. 0015); a fourth semiconductor region (15) located on the second semiconductor region, the fourth semiconductor region being of the first conductivity type (par. 0015); a gate electrode (40) facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction, the first direction being from the first electrode toward the first semiconductor region (par. 0016); a fifth semiconductor region (19), the fifth semiconductor region being of the first conductivity type, the fifth semiconductor region having a higher first-conductivity-type impurity concentration than the first semiconductor region (par. 0015); a sixth semiconductor region (21) located on the other portion of the first semiconductor region, the sixth semiconductor region being of the second conductivity type (par. 0027); a first region (23) located in the other portion of the first semiconductor region (par. 0027), and a second electrode (30) located on the second semiconductor region, the fourth semiconductor region, and the sixth semiconductor region (par. 0012) (Fig. 1).
Gejo fails to disclose a fifth semiconductor region located between an other portion of the first electrode and an other portion of the first semiconductor region and a concentration of crystal defects in the first region being greater than a concentration of crystal defects in a portion of the first semiconductor region surrounding the first region, the first region being located above the fifth semiconductor region and between the fifth semiconductor region and the second electrode in the first direction.
However, Ota teaches a fifth semiconductor region (15, par. 0044) located between an other portion of the first electrode (51) and an other portion of the first semiconductor region (11) and a concentration of crystal defects in the first region (14) being greater than a concentration of crystal defects in a portion of the first semiconductor region surrounding the first region (par. 0070, 0077), the first region being located above the fifth semiconductor region and between the fifth semiconductor region and the second electrode (52) in the first direction (Fig. 10).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Gejo with Ota by providing a first region with a greater concentration of crystal defects than the surrounding region and above the fifth semiconductor region in order to suppress the degradation of the characteristics of the body diode.
Regarding claim 15, Gejo discloses a device wherein the first semiconductor region (10) includes a first part (25), and a second part (11) located on the first part, an n-type impurity concentration of the second part is less than an n-type impurity concentration of the first part, and the first region is located in the first part (Fig. 1).
Claim 11 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Gejo in view of Ota as applied to claim 10 above, and further in view of Drobnis et al. (2003/0127645, hereafter Drobnis).
Regarding claim 11, Gejo, discussed above, fails to disclose a concentration of carbon in the first region being greater than a concentration of carbon in the first semiconductor region, a concentration of a first element in the first region being greater than a concentration of the first element in the first semiconductor region, the first element being at least one selected from the group consisting of platinum, gold, iron, copper, and nickel.
However, Drobnis teaches a concentration of carbon in the first region (25, Fig. 1, par. 0023) being greater than a concentration of carbon in the first semiconductor region (par. 0023-0024), a concentration of a first element in the first region being greater than a concentration of the first element in the first semiconductor region (par. 0023-0024), the first element being at least one selected from the group consisting of platinum, gold, iron, copper, and nickel (par. 0023, 0040).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Gejo with Drobnis by providing a greater concentration of carbon and the first element in the first region with a first element being of at least one of platinum, gold, iron, copper, and nickel because carbon imposes a specific profile such that a desired localized lifetime control is achieved via control of temperature of the device, and metal elements provide larger impurity atoms which are energetically favorable.
Regarding claim 23, Gejo fails to disclose a device wherein the first element is platinum.
However, Drobnis teaches a device according wherein the first element is platinum (par. 0040).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Gejo with Drobnis by providing the first region with a first element being platinum in order to increase agglomeration with other elements in the semiconductor.
Claims 16, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Gejo in view of Soeno (2014/0077253, hereafter Soeno).
Regarding claim 16, Gejo discloses a semiconductor device, comprising: a first electrode (20, par. 0012); a first semiconductor region (10) located on the first electrode, the first semiconductor region being of a first conductivity type (par. 0012); a second semiconductor region (13) located on a portion of the first semiconductor region, the second semiconductor region being of a second conductivity type (par. 0017); a third semiconductor region (17) located between a portion of the first electrode and the portion of the first semiconductor region, the third semiconductor region being of the second conductivity type (par. 0015); a fourth semiconductor region (15) located on the second semiconductor region, the fourth semiconductor region being of the first conductivity type (par. 0015); a gate electrode (40) facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction, the first direction being from the first electrode toward the first semiconductor region (par. 0013); a first region (23) located in the first semiconductor region (par. 0028), and a second electrode (20) located on the second semiconductor region and the fourth semiconductor region (par. 0012), wherein an element region (AR, par. 0023) and a termination region (TR, par. 0023) located around the element region are provided, the element region includes the portion of the first semiconductor region, and the termination region includes an other portion of the first semiconductor region (Fig. 1), wherein the first semiconductor region (10) includes a first part (25), and a second part (11) located on the first part, an n-type impurity concentration of the second part is less than an n-type impurity concentration of the first part, and the first region (23) is located in the first part (Fig. 1).
Gejo fails to disclose a concentration of crystal defects in the first region being greater than a concentration of crystal defects in a portion of the first semiconductor region surrounding the first region; the first region is located in the first part and includes a peak of a concentration profile of the crystal defects, and a portion of the first part is located between the first electrode and the peak in the first direction.
However, Soeno teaches a concentration of crystal defects in the first region (115) being greater than a concentration of crystal defects in a portion of the first semiconductor region (110) surrounding the first region (Fig. 1, par. 0028, 0037); the first region is located in the first part (112) and includes a peak of a concentration profile of the crystal defects (par. 0037), and a portion of the first part (113) is located between the first electrode (142) and the peak in the first direction (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Gejo with Soena by providing a first region with a peak concentration of crystal defects in the surrounding region and above the first electrode in order to suppress the degradation of the characteristics of the body diode.
Regarding claim 21, Gejo discloses a device wherein the first region (23, par. 0024) of the first semiconductor region (10) is located in the other portion (TR) of the first semiconductor region (Fig. 1).
Regarding claim 22, Gejo discloses a device further comprising: a fifth semiconductor region (21) located on the other portion of the first semiconductor region (Fig. 1), the fifth semiconductor region being of a second conductivity type (par. 0024).
Claims 20 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Gejo in view of Soeno as applied to claim 16 above, and further in view of Drobnis.
Regarding claim 20, Gejo, discussed above, fails to disclose a concentration of carbon in the first region being greater than a concentration of carbon in the first semiconductor region, a concentration of a first element in the first region being greater than a concentration of the first element in the first semiconductor region, the first element being at least one selected from the group consisting of platinum, gold, iron, copper, and nickel.
However, Drobnis teaches a concentration of carbon in the first region (25, Fig. 1, par. 0023) being greater than a concentration of carbon in the first semiconductor region (par. 0023-0024), a concentration of a first element in the first region being greater than a concentration of the first element in the first semiconductor region (par. 0023-0024), the first element being at least one selected from the group consisting of platinum, gold, iron, copper, and nickel (par. 0023, 0040).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Gejo with Drobnis by providing a greater concentration of carbon and the first element in the first region with a first element being of at least one of platinum, gold, iron, copper, and nickel because carbon imposes a specific profile such that a desired localized lifetime control is achieved via control of temperature of the device, and metal elements provide larger impurity atoms which are energetically favorable.
Regarding claim 24, Gejo fails to disclose a device wherein the first element is platinum.
However, Drobnis teaches a device according wherein the first element is platinum (par. 0040).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Gejo with Drobnis by providing the first region with a first element being platinum in order to increase agglomeration with other elements in the semiconductor.
Claim 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Gejo in view of Ota as applied to claim 10 above, and further in view of Kameyama et al. (2016/0254374, hereafter Kameyama).
Regarding claim 12, Gejo and Drobnis, discussed above, fail to disclose a device wherein a distance between the second electrode and the first region is greater than a distance between the first electrode and the first region.
However, Kameyama teaches a device wherein a distance between the second electrode (60) and the first region (70) is greater than a distance between the first electrode (62) and the first region (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Gejo and Drobnis with Kameyama by providing the first region closer to the electrode in order to suppress current attributed holes during turn-off time, thus reducing turn-off loss.
Regarding claim 13, Gejo discloses a device wherein the first semiconductor region (10) includes a first part (25), and a second part (11) located on the first part, an n-type impurity concentration of the second part is less than an n-type impurity concentration of the first part, and the first region (23) is located in the first part (Fig. 1).
Regarding claim 14, Gejo and Drobnis fail to disclose a device wherein a distance between the first electrode and the first region is greater than a distance between the second electrode and the first region.
However, Kameyama teaches a device wherein a distance between the first electrode (62) and the first region (72) is greater than a distance between the second electrode (60) and the first region (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Gejo and Drobnis with Kameyama by providing the first region closer to the electrode in order to suppress current attributed holes during turn-off time, thus reducing turn-off loss.
Claim 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Gejo in view of Soena as applied to claim 16 above, and further in view of Kameyama et al. (2016/0254374, hereafter Kameyama).
Regarding claim 17, Gejo and Drobnis, discussed above, fail to disclose a device wherein a distance between the second electrode and the first region is greater than a distance between the first electrode and the first region.
However, Kameyama teaches a device wherein a distance between the second electrode (60) and the first region (70) is greater than a distance between the first electrode (62) and the first region (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Gejo and Drobnis with Kameyama by providing the first region closer to the electrode in order to suppress current attributed holes during turn-off time, thus reducing turn-off loss.
Regarding claim 18, Gejo discloses a device wherein the first semiconductor region (10) includes a first part (25), and a second part (11) located on the first part, an n-type impurity concentration of the second part is less than an n-type impurity concentration of the first part, and the first region (23) is located in the first part (Fig. 1).
Regarding claim 19, Gejo and Drobnis fail to disclose a device wherein a distance between the first electrode and the first region is greater than a distance between the second electrode and the first region.
However, Kameyama teaches a device wherein a distance between the first electrode (62) and the first region (72) is greater than a distance between the second electrode (60) and the first region (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Gejo and Drobnis with Kameyama by providing the first region closer to the electrode in order to suppress current attributed holes during turn-off time, thus reducing turn-off loss.
Response to Arguments
Applicant’s arguments with respect to claims 10 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.M.B./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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