DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group (II) and Species (A and C1), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 30 March 2026.
Applicant’s election without traverse of Group I, Species B and C2 in the reply filed on 30 March 2026 is acknowledged.
Claim and Specification Status
The Examiner acknowledges the cancellation of non-elected claims 13-20 in the Applicant’s response dated 30 March 2026
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 8-9 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Durai Vishak Nirmal Ramaswamy (US 2020/0381290 A1; hereinafter “Ramaswamy”) in view of Yoshihiro Takaishi (US 2008/0283816 A1; hereinafter “Takaishi”).
Regarding Claim 1, Ramaswamy teaches an apparatus, comprising:
a first plurality of memory cells (FMC, annotated Fig. 20, para [0034] describes an edge capacitor 30 of an array of capacitors extending into and out of the page of Fig. 20 resulting in a plurality of memory cells FMC) extending in a first direction over a transistor array (20, annotated Fig. 20, para [0051] describes a transistor 20 in an array wherein the first plurality of memory cells FMC extend in a first direction over the transistor array 20) and coupled with a first digit line (78, annotated Fig. 20, para [0055] describes a bitline 78 which is coupled to the first memory cells FMC through channel region 72);
a second plurality of memory cells (SMC, annotated Fig. 20, para [0034] describes an internal capacitor 32 of an array of capacitors extending into and out of the page of Fig. 20 resulting in a plurality of memory cells SMC) extending in the first direction over the transistor array (20, annotated Fig. 20, para [0051] describes a transistor 20 in an array wherein the second plurality of memory cells SMC extend in a first direction over the transistor array 20) and coupled with a second digit line (78, annotated Fig. 20, para [0055] describes a bitline 78 which is coupled to the second memory cells SMC through channel region 72 wherein one of the plurality of second memory cells SMC may be coupled with a second digit line 78 in a direction into the page of Fig. 20 as shown by BL-2 in Fig. 10); and
a void (56, Fig. 20, para [0043] describes void regions between memory cells 18).
PNG
media_image1.png
563
853
media_image1.png
Greyscale
Ramaswamy fails to explicitly disclose a first plurality of memory cells on a first sidewall of a first liner structure; a second plurality of memory cells on a first sidewall of a second liner structure; and a void between the first liner structure and the second liner structure, the void exposing a second sidewall of the first liner structure and a second sidewall of the second liner structure.
However, Takaishi teaches a similar apparatus, comprising:
a first plurality of memory cells (CP, Fig. 40, para [0078] describes a plurality of capacitors CP of a DRAM device) on a first sidewall of a first liner structure (82, Fig. 40, para [0101] describes a sidewall insulation film 82 wherein the first memory cells CP are formed on a first sidewall of the liner structure 82);
a second plurality of memory cells (ARY, Fig. 41, para [0109] describes wherein a second plurality of memory cells CP are comprised on an opposite side of an opening 62A from the first plurality of memory cells CP) on a first sidewall of a second liner structure (82, Fig. 40, para [0101] describes a sidewall insulation film 82 wherein the second memory cells CP are formed on a first sidewall of the second liner structure 82); and
a void between the first liner structure and the second liner structure (62A and 60, Fig. 40 and Fig. 41, para [0103] describes wherein a cavity 60 is formed in an opening area 62a wherein opening 62a is between the first liner structure 82 and the second liner structure 82), the void exposing a second sidewall of the first liner structure and a second sidewall of the second liner structure (60, Fig. 40, para [0103] wherein Fig. 40 depicts void 60 extending to a second sidewall of the first and second liner structures 82 wherein the second sidewall is opposite capacitor elements 51-53 resulting in the void 60 exposing a second sidewall of the first liner structure 82 and a second sidewall of the second liner structure 82).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Ramaswamy with Takaishi to further disclose an apparatus comprising a first and second liner structure between a first plurality of memory cells, a second plurality of memory cells and a void in order to provide the advantage of preventing damage to the memory cell structure on first sidewalls of the liner structure during a cavity, or void, forming process (Takaishi, para [0101]).
Regarding Claim 2, the combination of Ramaswamy and Takaishi teaches the apparatus of claim 1, wherein:
a first memory cell of the first plurality of memory cells (Ramaswamy, FMC, annotated Fig. 20 depicts a first memory cell of the first plurality of memory cells FMC) comprises a first electrode having a first sidewall on the first liner structure (Ramaswamy, 24, annotated Fig. 20, para [0021] describes a first electrode 24 of the first memory cell of the first plurality of memory cells FMC wherein upon combining the liner 82 of Takaishi with the first electrode 24 of Ramaswamy, the first electrode 24 of Ramaswamy will have a first sidewall on the first liner structure 82 of Takaishi) and a second sidewall coupled with a first ferroelectric layer (Ramaswamy, 28, annotated Fig. 20, para [0026] describes a capacitor insulative material 28 that may comprise a ferroelectric insulative material coupled to a second sidewall of the first electrode 24); and
a second memory cell of the second plurality of memory cells (Ramaswamy, SMC, annotated Fig. 20 depicts a second memory cell of the second plurality of memory cells SMC) comprises a second electrode having a third sidewall on the second liner structure (Ramaswamy, 24, annotated Fig. 20, para [0021] describes an electrode 24 of the second memory cell of the second plurality of memory cells SMC wherein upon combining the liner 82 of Takaishi with the second electrode 24 of Ramaswamy, the second electrode 24 of Ramaswamy will have a third sidewall on the second liner structure 82 of Takaishi) and a fourth sidewall coupled with a second ferroelectric layer (Ramaswamy, 28, annotated Fig. 20, para [0026] describes a capacitor insulative material 28 that may comprise a ferroelectric insulative material coupled to a fourth sidewall of the second electrode 24 of the second memory cell of the second plurality of memory cells SMC).
Regarding Claim 4, the combination of Ramaswamy and Takaishi teaches the apparatus of claim 1, further comprising:
a third plurality of memory cells (Ramaswamy, TMC, annotated Fig. 20 II, para [0034] describes an internal capacitor 32 of an array of capacitors extending into and out of the page of Fig. 20 resulting in a third plurality of memory cells TMC) on a sidewall of a third liner structure (Takaishi, 82, Fig. 40, para [0101] describes a sidewall insulation film 82 wherein upon combining Ramaswamy with Takaishi, a third liner structure 82 of Takaishi would be on a sidewall of the plurality of third memory cells TMC of Ramaswamy) extending in the first direction over the transistor array (20, annotated Fig. 20, para [0051] describes a transistor 20 in an array wherein the third plurality of memory cells TMC extends in a first direction over the transistor array 20), the third plurality of memory cells and the first plurality of memory cells coupled with a first plate line (Ramaswamy, FMC and TMC, annotated Fig. 20 and annotated Fig. 20 II, para [0039] describes a conductive plate 48 wherein a first conductive plate line 48 can be seen coupled to both the third plurality of memory cells TMC and the first plurality of memory cells TCM), wherein the third plurality of memory cells is further coupled with a third digit line (Ramaswamy, 78, annotated Fig. 20, para [0055] describes a bitline 78 which is coupled to the third memory cells TMC through channel region 72 wherein at least one of the plurality of third memory cells TMC may be coupled with a third digit line 78 in a direction into or out of the page of Fig. 20 as shown by BL-3 in Fig. 10).
PNG
media_image2.png
563
806
media_image2.png
Greyscale
Regarding Claim 8, the combination of Ramaswamy and Takaishi teaches the apparatus of claim 4, wherein:
a first memory cell of the first plurality of memory cells (Ramaswamy, FMC, annotated Fig. 20 depicts a first memory cell of the first plurality of memory cells FMC) comprises a first electrode having a first sidewall on the first liner structure (Ramaswamy, 24, annotated Fig. 20, para [0021] describes a first electrode 24 of the first memory cell of the first plurality of memory cells FMC wherein upon combining the liner 82 of Takaishi with the first electrode 24 of Ramaswamy, the first electrode 24 of Ramaswamy will have a first sidewall on the first liner structure 82 of Takaishi) and a second sidewall coupled with a first ferroelectric layer (Ramaswamy, 28, annotated Fig. 20, para [0026] describes a capacitor insulative material 28 that may comprise a ferroelectric insulative material coupled to a second sidewall of the first electrode 24); and
a second memory cell of the third plurality of memory cells (Ramaswamy, TMC, annotated Fig. 20 II depicts a second memory cell of the third plurality of memory cells TMC) comprises a second electrode having a third sidewall on the second liner structure (Ramaswamy, 24, annotated Fig. 20, para [0021] describes an electrode 24 of the second memory cell of the third plurality of memory cells TMC wherein upon combining the liner 82 of Takaishi with the second electrode 24 of Ramaswamy, the second electrode 24 of Ramaswamy will have a third sidewall on the second liner structure 82 of Takaishi) and a fourth sidewall coupled with a second ferroelectric layer (Ramaswamy, 28, annotated Fig. 20, para [0026] describes a capacitor insulative material 28 that may comprise a ferroelectric insulative material coupled to a fourth sidewall of the second electrode 24 of the second memory cell of the third plurality of memory cells TMC).
Regarding Claim 9, the combination of Ramaswamy and Takaishi teaches the apparatus of claim 8, wherein the first plate line extends between the second sidewall and the fourth sidewall (48, F and S, annotated Fig. 20 III depicts wherein the first plate line 48 extends in a horizontal direction between the second sidewall S and the fourth sidewall F).
PNG
media_image3.png
532
811
media_image3.png
Greyscale
Regarding Claim 11, the combination of Ramaswamy and Takaishi teaches the apparatus of claim 1, wherein the void exposes at least a portion of a surface of the transistor array (56 and 62, Fig. 20, para [0048] describes wherein transistors 20 are supported in a support structure 62 wherein the void 56 exposes a top surface of the transistor array support structure 62).
Regarding Claim 12, the combination of Ramaswamy and Takaishi teaches the apparatus of claim 1, wherein the transistor array comprises:
a set of transistors arranged in one or more columns extending in the first direction and one or more rows extending in a second direction (22 and 20, Fig. 2, para [0020] describes wherein transistors 20 are arranged in an array including at least one column in the first direction as shown in Fig. 20 and at least one row extending in a second direction as shown in Fig. 20), the set of transistors comprising a first column of transistors having contacts coupled with the first plurality of memory cells (20, annotated Fig. 20, para [0020] describes wherein transistors 20 are electrically coupled with capacitors 18 wherein the first plurality of memory cells FMC are coupled to a first column of transistors 20 through a source/drain region 68 contacting the first plurality of memory cells FMC) and a second column of transistors having contacts coupled with the second plurality of memory cells (20, annotated Fig. 20, para [0020] describes wherein transistors 20 are electrically coupled with capacitors 18 wherein the second plurality of memory cells SMC are coupled to a second column of transistors 20 through a source/drain region 68 contacting the second plurality of memory cells SMC).
Claims 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Durai Vishak Nirmal Ramaswamy (US 2020/0381290 A1; hereinafter “Ramaswamy”) in view of Yoshihiro Takaishi (US 2008/0283816 A1; hereinafter “Takaishi”) and in view of the following arguments:
Regarding Claim 3, the combination of Ramaswamy and Takaishi teaches the apparatus of claim 2, wherein a first plate line extending in the first direction is coupled with the first ferroelectric layer (Ramaswamy, 48, annotated Fig. 20 and Fig. 21, para [0039] describes a conductive plate 48 wherein resulting first plate line 48 extending in the first direction is coupled with the first ferroelectric layer 28 of the first memory cell of the first plurality of memory cells FMC).
Ramaswamy and Takaishi fail to explicitly disclose a second plate line extending in the first direction is coupled with the second ferroelectric layer.
However, Ramaswamy teaches in a further embodiment, a second plate line extending in the first direction is coupled with the second ferroelectric layer (Ramaswamy, 48, annotated Fig. 20 and Fig. 21, para [0039] describes the conductive plate 48 wherein para [0039] further describes that it may be preferable to have two or more conductive plates 48 as shown in a similar embodiment in Fig. 21 when the insulative material 28 is ferroelectric insulating material wherein a second plate line 48 extending in the first direction is coupled with the second ferroelectric layer 28 of the second memory cell of the second plurality of memory cells SMC when using the plurality of conductive plates as shown in Fig. 21).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Ramaswamy and Takaishi with the further embodiment of Ramaswamy to further disclose an apparatus comprising a second plate line extending in the first direction coupled with a second ferroelectric layer in order to provide the advantage of providing multiple plates for ferroelectric insulative materials to be coupled to as is preferable (Ramaswamy, para [0039]) and to further provide the well-known advantage of providing two separate conductive plates so that different voltages can be supplied to different conductive plates and different memory cells enabling a wider range of uses for the memory apparatus.
Regarding Claim 10, the combination of Ramaswamy and Takaishi teaches the apparatus of claim 1, wherein the void exposes at least a portion of a lower surface of a first plate line coupled with the first plurality of memory cells (56, annotated Fig. 20, para [0043] describes void regions 56 wherein the void regions 56 expose at least a portion of a lower surface of a first plate line 48 coupled with the first plurality of memory cells FMC as shown in annotated Fig. 20).
Ramaswamy and Takaishi fail to explicitly disclose wherein the void exposes at least a portion of a lower surface of a second plate line coupled with the second plurality of memory cells.
However, Ramaswamy teaches in a further embodiment, wherein the void exposes at least a portion of a lower surface of a second plate line coupled with the second plurality of memory cells (56, annotated Fig. 20 and Fig. 21, para [0039] describes the conductive plate 48 wherein para [0039] further describes that it may be preferable to have two or more conductive plates 48 as shown in a similar embodiment in Fig. 21 when the insulative material 28 is ferroelectric insulating material further wherein upon separating the first conductive plate 48 into two plates as shown in Fig. 21, the second conductive plate line 48 would be coupled with the second plurality of memory cells SMC as shown in annotated Fig. 20 and Fig. 21 and further wherein the void 56 would further expose at least a portion of a lower surface of the second plate line 48 coupled with the second plurality of memory cells SMC).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Ramaswamy and Takaishi with the further embodiment of Ramaswamy to further disclose an apparatus comprising a void exposing at least a portion of a lower surface of a second plate line coupled with a second plurality of memory cells in order to provide the advantage of providing multiple plates for ferroelectric insulative materials to be coupled to as is preferable (Ramaswamy, para [0039]) and to further provide the well-known advantage of providing two separate conductive plates so that different voltages can be supplied to different conductive plates and different memory cells enabling a wider range of uses for the memory apparatus.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Durai Vishak Nirmal Ramaswamy (US 2020/0381290 A1; hereinafter “Ramaswamy”) in view of Yoshihiro Takaishi (US 2008/0283816 A1; hereinafter “Takaishi”) and in further view of Giorgio Servalli et al. (US 2021/0210491 A1; hereinafter “Servalli”).
Regarding Claim 5, the combination of Ramaswamy and Takaishi teaches the apparatus of claim 4, further comprising: a fourth plurality of memory cells (Ramaswamy, FPMC, annotated Fig. 20 II, para [0034] describes an internal capacitor 32 of an array of capacitors extending into and out of the page of Fig. 20 resulting in a fourth plurality of memory cells FPMC) on a sidewall of a fourth liner structure (Takaishi, 82, Fig. 40, para [0101] describes a sidewall insulation film 82 wherein upon combining Ramaswamy with Takaishi, a fourth liner structure 82 of Takaishi would be on a sidewall of the plurality of fourth memory cells FPMC of Ramaswamy) extending in the first direction over the transistor array (20, annotated Fig. 20, para [0051] describes a transistor 20 in an array wherein the fourth plurality of memory cells FPMC extends in a first direction over the transistor array 20), the fourth plurality of memory cells coupled with the first plate line (Ramaswamy, FPMC, annotated Fig. 20 and annotated Fig. 20 II, para [0039] describes a conductive plate 48 wherein a first conductive plate line 48 can be seen coupled to the fourth plurality of memory cells FPMC).
PNG
media_image4.png
563
806
media_image4.png
Greyscale
Ramaswamy and Takaishi fail to explicitly disclose wherein the fourth plurality of memory cells is further coupled with a fourth digit line.
However, Servalli teaches a similar apparatus wherein the fourth plurality of memory cells is further coupled with a fourth digit line (FPMC2 and FDL, annotated Fig. 22B, para [0101] describes wherein each of the memory cells 80 such as the fourth plurality of memory cells FPMC2 as shown in annotated Fig. 22B is uniquely coupled to one of the digit lines 24 such as the fourth digit line FDL as shown in annotated Fig. 22B).
PNG
media_image5.png
630
562
media_image5.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Ramaswamy and Takaishi with Servalli to further disclose an apparatus wherein a fourth plurality of memory cells is further coupled with a fourth digit line in order to provide the well-known advantage of providing a capacitor that can be uniquely addressed using a unique digit line coupled to it so that memory cells may store information properly and avoid overwriting data or storing data in undesirable locations (Servalli, para [0126]).
Regarding Claim 6, the combination of Ramaswamy, Takaishi and Servalli teaches the apparatus of claim 5, further comprising:
a second void between the third liner structure and the fourth liner structure (Ramaswamy, SV, TMC and FPMC, annotated Fig. 20 II, annotated Fig 20 IV and annotated Fig. V depicts wherein the third plurality of memory cells TMC and fourth plurality of memory cells FPMC are adjacent to each other in a horizontal direction wherein upon combining the liner 82 of Takaishi with the plurality of memory cells of Ramaswamy, the third liner would be on a sidewall of the third plurality of memory cells TMC facing the fourth plurality of memory cells FPMC and the fourth liner would be on a sidewall of the fourth plurality of memory cells FPMC facing the third plurality of memory cells TMC with a second void SV therebetween), the second void exposing a second sidewall of the third liner structure and a second sidewall of the fourth liner structure (Ramaswamy, 56, annotated Fig. 20 II, annotated Fig 20 IV and annotated Fig. V depicts wherein the second void SV would be between the third plurality of memory cells TMC and fourth plurality of memory cells FPMC and further wherein upon combining the liner 82 of Takaishi with the plurality of memory cells of Ramaswamy, the second void 56 would expose a second sidewall of the third liner structure opposite the electrode 24 and a second sidewall of the fourth liner structure opposite the electrode 24).
PNG
media_image6.png
538
790
media_image6.png
Greyscale
Regarding Claim 7, the combination of Ramaswamy, Takaishi and Servalli teaches the apparatus of claim 6, wherein the second void exposes a portion of a lower surface of the first plate line (Ramaswamy, SV and 48, annotated Fig. V depicts wherein the second void SV exposes a portion of a lower surface of the first plate line 48).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights