DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 6, 15, 16, 17, 18, 19, and 20 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected device, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on April 10, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 12, line 4 recites the limitation “a first upper chip bonding wire connecting the first middle upper chip pad to the second upper chip pad,” (italics added). However, in keeping with the limitation pattern of claim 12 and Drawings 1, 4, 6, and 9 of the disclosure, the limitation clearly intends to read, “a first upper chip bonding wire connecting the first middle upper chip pad to the first upper chip pad.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 3, 4, 5, 7, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bang et al. (2022/0336420, hereafter Bang).
Regarding claim 1, Bang discloses a semiconductor package, comprising: a control chip (320, par. 0037) and a memory stack mounted on a substrate (100, par. 0016), wherein the memory stack includes a first memory stack (220, par. 0025) and a second memory stack (230, par. 0025) stacked over the first memory stack; and first (226A) and second (236B) stack bonding wires (par. 0018, 0021), wherein the control chip includes a first channel pad (324 right, par. 0038) and a second channel pad (324 left, par. 0038), wherein the substrate includes: a first electrical path including: a first bonding pad (104A-2, par. 0017) electrically connected to the first channel pad, a first substrate interconnection (108A, par. 0016) electrically connected to the first bonding pad, and a first bond finger (214A, par. 0020) electrically connected to the first substrate interconnection; and a second electrical path including: a second bonding pad (104B-2, par. 0017) electrically connected to the second channel pad, a second substrate interconnection (108B, par. 0016) electrically connected to the second bonding pad, and a second bond finger (214B, par. 0020) electrically connected to the second substrate interconnection, and wherein: the first stack bonding wire electrically connects the first bond finger to the first memory stack, the second stack bonding wire electrically connects the second bond finger to the second memory stack, the first stack bonding wire is shorter than the second stack bonding wire, and the first electrical path is longer than the second electrical path (Fig. 1).
Regarding claim 2, Bang discloses a semiconductor package wherein: the substrate includes a chip mounting area (Fig. 1 right) where the control chip is mounted and a stack mounting area (Fig. 1 left) where the first and second memory stacks are mounted, and the first bonding pad (104A-2, par. 0017) and the second bonding pad (104B-2, par. 0017) are disposed in the chip mounting area, and the first bonding pad is farther from the stack mounting area than the second bonding pad (Fig. 1).
Regarding claim 3, Bang discloses a semiconductor package wherein the substrate further includes: a first substrate via (108A right) disposed in the chip mounting area to electrically connect the first bonding pad (104A-2) to the first substrate interconnection (108A); and a second substrate via (108A left) disposed in the stack mounting area to electrically connect the first substrate interconnection to the first bond finger (214A) (Fig. 1).
Regarding claim 4, Bang discloses a semiconductor package wherein a first electrical connection distance of the first substrate interconnection (108A) from a portion connected to the first substrate via to a portion connected to the second substrate via is longer than a second electrical connection length distance of the second substrate interconnection (108B) from a portion connected to the second bonding pad (104B-2) to a portion connected to the second bond finger (214B) (Fig. 1).
Regarding claim 5, Bang discloses a semiconductor package further comprising: a third substrate via (108B left) electrically connecting the second bonding pad and the second substrate interconnection; and a fourth substrate via (108B right) electrically connecting the second substrate interconnection to the second bond finger, wherein vertical lengths of the first and second substrate vias (108A left/right) are greater than vertical lengths of the third and fourth substrate vias (Fig. 1).
Regarding claim 7, Bang discloses a semiconductor package further comprising: a first chip connector (340 center left) electrically connecting the first channel pad (324 right) to the first bonding pad (104A-2); and a second chip connector (340 left) electrically connecting the second channel pad (324 left) to the second bonding pad (104B-2), wherein an electrical path from the first chip connector to the first bond finger (214A) is longer than an electrical path from the second chip connector to the second bond finger (214B) (Fig. 1, par. 0036).
Regarding claim 8, Bang discloses a semiconductor package further comprising: a first channel wire (326 right) electrically connecting the first channel pad (324 right) to the first bonding pad (104A-2); and a second channel wire (326 left) electrically connecting the second channel pad (324 left) to the second bonding pad (104B-2), wherein an electrical path from the first channel pad to the first bond finger is longer than an electrical path from the second channel pad to the second bond finger (Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Bang in view of Oh et al. (2018/0005994, hereafter Oh).
Regarding claim 9, Bang fails to disclose a semiconductor package wherein the first memory stack includes a first lower memory chip, a first middle lower memory chip, a first middle upper memory chip, and a first upper memory chip that are stacked in a staircase, wherein: the first lower memory chip includes a first lower chip pad, the first middle lower memory chip includes a first middle lower chip pad, first middle upper memory chip includes a first middle upper chip pad, the first upper memory chip includes a first upper chip pad, and the first stack bonding wire connects one of the first middle lower chip pad and the first middle upper chip pad to the first bond finger, wherein the second memory stack includes a second lower memory chip, a second middle lower memory chip, a second middle upper memory chip, and a second upper memory chip that are stacked in a staircase, wherein: the second lower memory chip includes a second lower chip pad, the second middle lower memory chip includes a second middle lower chip pad, the second middle upper memory chip includes a second middle upper chip pad, the second upper memory chip includes a second upper chip pad, and the second stack bonding wire connects one of the second middle lower chip pad and the second middle upper chip pad to the second bond finger.
However, Oh teaches a semiconductor package wherein the first memory stack includes a first lower memory chip (120-1), a first middle lower memory chip (120-2), a first middle upper memory chip (120-3), and a first upper memory chip (120-4) that are stacked in a staircase, wherein: the first lower memory chip includes a first lower chip pad, the first middle lower memory chip includes a first middle lower chip pad, first middle upper memory chip includes a first middle upper chip pad, the first upper memory chip includes a first upper chip pad, and the first stack bonding wire connects one of the first middle lower chip pad and the first middle upper chip pad (pads 151, par. 0038) to the first bond finger (101-1), wherein the second memory stack includes a second lower memory chip (140-1), a second middle lower memory chip (140-2), a second middle upper memory chip (140-3), and a second upper memory chip (140-4) that are stacked in a staircase, wherein: the second lower memory chip includes a second lower chip pad, the second middle lower memory chip includes a second middle lower chip pad, the second middle upper memory chip includes a second middle upper chip pad, the second upper memory chip includes a second upper chip pad (pads 161, par. 0062), and the second stack bonding wire connects one of the second middle lower chip pad and the second middle upper chip pad to the second bond finger (101-3) (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Bang with Oh by implementing successive chips in staircase arrangement with each subsequently connected with wires in order to increase connectivity between chips by providing a landing pad for interconnects.
Regarding claim 12, Bang fails to disclose a semiconductor package further comprising: a first lower chip bonding wire connecting the first lower chip pad to the first middle lower chip pad, a first middle chip bonding wire connecting the first middle lower chip pad to the first middle upper chip pad, a first upper chip bonding wire connecting the first middle upper chip pad to the first upper chip pad, a second lower chip bonding wire connecting the second lower chip pad to the second middle lower chip pad, a second middle chip bonding wire connecting the second middle lower chip pad to the second middle upper chip pad, and a second upper chip bonding wire connecting the second middle upper chip pad to the second upper chip pad, wherein the first upper chip pad and the second lower chip pad are not directly connected to each other.
However, Oh teaches a semiconductor package further comprising: a first lower chip bonding wire connecting the first lower chip pad to the first middle lower chip pad, a first middle chip bonding wire connecting the first middle lower chip pad to the first middle upper chip pad, a first upper chip bonding wire connecting the first middle upper chip pad to the first upper chip pad (pads 151, wires 150), a second lower chip bonding wire connecting the second lower chip pad to the second middle lower chip pad, a second middle chip bonding wire connecting the second middle lower chip pad to the second middle upper chip pad, and a second upper chip bonding wire connecting the second middle upper chip pad to the second upper chip pad (pads 161, wires 160), wherein the first upper chip pad and the second lower chip pad are not directly connected to each other (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Bang with Oh by connecting each subsequent pad with successive wires and not connecting the first stack directly to the other in order to increase connectivity between chips by providing wire bonding that supports universal communication.
Claims 10, 11, 13, and 14 is rejected under 35 U.S.C. 103 as being unpatentable over Bang in view of Oh as applied to claim 9 above, and further in view of Chung et al. (2022/0068887, hereafter Chung).
Regarding claim 10, Bang discloses a semiconductor package wherein the first bond finger (214A) and the second bond finger (214B) are disposed not to be aligned with the first straight line (Fig. 2).
Bang fails to disclose a semiconductor package wherein: in a top view, the first lower chip pad, the first middle lower chip pad, the first middle upper chip pad, the first upper chip pad, the second lower chip pad, the second middle lower chip pad, the second middle upper chip pad, and the second upper chip pad are disposed to be aligned on a first straight line.
However, Chung teaches a semiconductor package wherein: in a top view, the first lower chip pad, the first middle lower chip pad, the first middle upper chip pad, the first upper chip pad, the second lower chip pad, the second middle lower chip pad, the second middle upper chip pad, and the second upper chip pad are disposed to be aligned on a first straight line (pads 710, Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Bang with Chung by implementing subsequent chip pads in a straight line in order to simplify the design process, optimize area efficiency, and provide pitch-matching.
Regarding claim 11, Bang discloses a semiconductor package wherein: the first bond finger (214A) is disposed to be spaced apart from the first straight line in a first direction, the second bond finger (214B) is disposed to be spaced apart from the first straight line in a second direction, and the first direction and the second direction are opposite directions to each other (par. 0020).
Regarding claim 13, Bang discloses a first stack bonding wire (226A) and a second stack bonding wire (236B) being disposed to be diagonal to a straight line (Fig. 2, par. 0021).
Bang fails to disclose a semiconductor package wherein: the first lower chip bonding wire, the first middle chip bonding wire, the first upper chip bonding wire, the second lower chip bonding wire, the second middle chip bonding wire, and the second upper chip bonding wire are disposed to form a straight line.
However, Chung teaches a semiconductor package wherein: the first lower chip bonding wire, the first middle chip bonding wire, the first upper chip bonding wire, the second lower chip bonding wire, the second middle chip bonding wire, and the second upper chip bonding wire are disposed to form a straight line (wires 750, Fig. 2, par. 0039).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Bang with Chung by disposing bonding wires in a straight line in order to minimize physical distance and thus propagation delay.
Regarding claim 14, Bang discloses a semiconductor package wherein: the first stack bonding wire (226A) is disposed to extend from the straight line in a first diagonal direction, and the second stack bonding wire (236B) is disposed to extend from the straight line in a second diagonal direction, and the first diagonal direction is different from the second diagonal direction (Fig. 2, par. 0020).
Conclusion
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/C.M.B./ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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