DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, 6, 8, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Funaya et al. (2015/0162395, hereafter Funaya ‘395) in view of Kuwabara et al. (2020/0043847).
Regarding claim 1, Funaya ‘395 discloses a semiconductor device comprising: a semiconductor substrate (1); a multilayer wiring layer (M1, M2, M3) formed on the semiconductor substrate; a lower inductor (Ia, par. 0066) formed in the multilayer wiring layer; … an upper inductor (Ib) formed on the multilayer wiring layer and configured to be applied with a second potential different from the first potential (par. 0066-0067); an inorganic insulating film (IL4) formed on the multilayer wiring layer and the first wiring…; and an organic insulating film (PI1) formed on the inorganic insulating film and disposed so as to cover the inorganic insulating film located between the first wiring and the upper inductor in plan view, wherein between the first wiring and the upper inductor, an opening portion (St1, par. 0079) exposing a part of an upper surface of the inorganic insulating film is formed in the organic insulating film (Fig. 38).
Funaya ‘395 fails to disclose a first wiring formed on the multilayer wiring layer so as to be in contact with an uppermost layer of the multilayer wiring layer and configured to be applied with a first potential; and an insulating film formed on the upper inductor.
However, Kuwabara teaches a first wiring (FM4, Fig. 14) formed on the multilayer wiring layer (FML, Fig. 3, par. 0078) so as to be in contact with an uppermost layer (par. 0077) of the multilayer wiring layer and configured to be applied with a first potential (par. 0079), and an insulating film (CVF, Fig. 3, par. 0078) formed on the upper inductor (FID, par. 0070).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Funaya ‘395 with Kuwabara by including a first wiring in contact with the top layer of the wiring and an insulating layer on top of the inductor in order to provide external electrical connections or redistribution pathways, while the insulator prevents degradation and shorting across the inductor.
Regarding claim 2, Funaya ‘395 discloses a semiconductor device wherein the opening portion (St1) is formed so as to surround the upper inductor (Ib) in plan view (Fig. 39).
Regarding claim 4, Funaya ‘395 discloses a semiconductor device wherein the opening portion (St3) is formed so as to include the upper inductor (Ib) (Fig. 39).
Regarding claim 5, Funaya ‘395 fails to disclose a semiconductor device wherein the opening portion is formed so as to include a part of the first wiring.
However, Kuwabara teaches a semiconductor device wherein the opening portion (VH2) is formed so as to include a part of the first wiring (SM4, par. 0106).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Funaya ‘395 with Kuwabara by including the first wiring in the opening in order to prevent electrical breakdown along interfaces of the device.
Regarding claim 6, Funaya ‘395 discloses a semiconductor device wherein the semiconductor device comprises: a first semiconductor chip (CH2, Fig. 39, par. 0066) including: the first wiring (M1, Fig. 38) ; a circuit electrically connected to the first wiring (par. 0066); the upper inductor (Ib; Fig. 38, par. 0066); and the organic insulating film (PI1, Fig. 38); and a second semiconductor chip (CH1, par. 0067) including a circuit configured to supply the second potential to the inductor (Ib; par. 0067).
Regarding claim 8, Funaya ‘395 fails to disclose a semiconductor device wherein the first wiring is disposed so as to be in contact with an uppermost layer of the multilayer wiring layer, and wherein the upper inductor is disposed so as to be in contact with the uppermost layer.
However, Kuwabara teaches a semiconductor device wherein the first wiring (FM4, Fig. 14) is disposed so as to be in contact with an uppermost layer of the multilayer wiring layer (FML, Fig. 3, par. 0078), and wherein the upper inductor (FID, par. 0070) is disposed so as to be in contact with the uppermost layer (Fig. 3).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Funaya ‘395 with Kuwabara by including a first wiring and inductor in contact with the uppermost layer in order to provide external electrical connections or redistribution pathways and minimize parasitic capacitance and energy loss and reducing resistance.
Regarding claim 9, Funaya ‘395 discloses a semiconductor device comprising: a pad opening portion formed to penetrate through the organic insulating film (PI3) and the inorganic insulating film (IL4) in order to expose a pad (PD2) connectable to a bonding wire (par. 0065), wherein the opening portion is different from the pad opening portion (Fig. 37).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Funaya ‘395 in view of Kuwabara et al. (20200043847) as applied to claim 1 above and further in view of Shiroi et al. (2022/0223508, hereafter Shiroi).
Regarding claim 3, Funaya ‘395 discloses an upper inductor (Ib) between opening portions (St1, Fig. 39) in plan view.
Funaya ‘395 fails to disclose a semiconductor device wherein the opening portion is configured by: a first opening portion extending in a first direction; a second opening portion extending in a second direction intersecting with the first direction; a third opening portion extending in the first direction and facing the first opening portion; and a fourth opening portion extending in the second direction and facing the second opening portion, wherein the first opening portion and the second opening portion are spaced apart from each other in plan view, wherein the first opening portion and the fourth opening portion are spaced apart from each other in plan view, wherein the third opening portion and the second opening portion are spaced apart from each other in plan view, and wherein the third opening portion and the fourth opening portion are spaced apart from each other in plan view.
However, Shiroi teaches a semiconductor device wherein the opening portion is configured by: a first opening portion extending in a first direction (HP2, top left); a second opening portion extending in a second direction intersecting with the first direction (HP2, top right); a third opening portion extending in the first direction and facing the first opening portion (HP2, bottom left); and a fourth opening portion extending in the second direction and facing the second opening portion (HP2, bottom right), wherein the first opening portion and the second opening portion are spaced apart from each other in plan view, wherein the first opening portion and the fourth opening portion are spaced apart from each other in plan view, wherein the third opening portion and the second opening portion are spaced apart from each other in plan view, and wherein the third opening portion and the fourth opening portion are spaced apart from each other in plan view (Fig. 8).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Funaya ‘395 with Shiroi by implementing four opening portions that face each other and are space apart in order to provide improved connectivity via a low resistance path for electrical current and to prevent residual current from the inductor and reduce energy dissipation.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Funaya ‘395 in view of Kuwabara as applied to claim 1 above and further in view of Funaya et al. (2016/0035672, hereafter Funaya ‘672).
Regarding claim 7, Funaya ‘395 discloses a semiconductor device wherein the upper inductor includes: a first pad (PD2) connectable to a first bonding wire (par. 0065); and a second wiring (W, par. 0065) connected to the first pad (Fig. 1).
Funaya ‘395 fails to disclose a width of the second wiring being greater than a width of the first wiring.
However, Funaya ‘672 teaches a width of the second wiring being greater than a width of the first wiring (par.0262).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Funaya ‘395 with Funaya ‘672 by making the width of the second wiring greater than the first wiring in order to reduce wiring resistance.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (572) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.M.B./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights