Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Request for Continued Examination filed February 4, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 10, 17
b. Pending: 1-21
Claim 21 is new.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on December 15, 2025 and April 21, 2026 were filed after the mailing date of the Allowance on November 4, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: A DEVICE, CONTROLLER, AND METHOD FOR PERFORMING SCAN PRIOR TO REFRESH
Claim Objections
Claims 5 and 15 are objected to because of the following informalities:
Regarding claim 5, on p.3, lines 4-5, make the following change because it does not make sense to say “status information comparing information”:
“wherein the result of the operation includes status information that is a result of comparing information related to the plurality of memory blocks,
which was acquired by the operation, with a threshold value.”
Regarding claim 15, in the second to last line on page 5, claim 15 teaches “the number of bit error”. Please change to “the number of bit errors”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3, 6, 10, 12, 15, and 19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention.
There is no support in the disclosure for a device health information relating to a combination of “a number of bit errors” with any of the other listed parameters (i.e.: read count, erase count, or failed bit count). In the Specification, “the number of error bits” is only mentioned twice, in paras. [0053] of the Summary section and [0053] of the Brief Description of the Drawings section. In both paragraphs, error bits are discussed in relation to ECC circuit correction operations, not refresh scan or refresh operations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Suzuki et al. (US Pub. 20180300071 A1).
Regarding independent claim 1, Suzuki discloses a controller (Fig. 1: memory controller 5; [0019]) for controlling a nonvolatile memory device (NAND flash memory; [0019]), the controller comprising:
a host interface (host interface 3; [0043]) configured to receive a refresh scan request from a host device ([0043]: the host I/F 3 transmits the user data read from the NAND 10, a response from the control unit 20, and the like to the host 1; [0074]: FIG. 8 is a flowchart that illustrates the refreshing process executed by the refresh control unit 24…The refresh control unit 24 calculates the number of error bits of a block based on information notified from the ECC unit 23 at the time of executing a reading process or patrol reading based on a read command transmitted from the host 1);
a processor (refresh control unit 24) configured to control the nonvolatile memory device to perform an operation on a plurality of memory blocks in response to the refresh scan request ([0077] provides examples of the refresh control unit determining whether to perform a refresh); and
a memory interface (memory interface 40; [0043]) configured to transfer a refresh command for performing a refresh operation to the nonvolatile memory device in response to a refresh request received from the host device ([0043]: The memory I/F 40 directly controls the NAND 10 based on a instruction from the control unit 20),
wherein a result of the operation includes device health information relating to at least one of a read count, an erase count, a number of bit errors, a failed bit count, or any combination thereof ([0071]: As the refreshing parameters, for example, numerical values representing the degrees of error of a block such as the number of error bits of the block…are used. In addition, as the refreshing parameter, the number of times of executing erasing data of a block, the number of times of reading data of a block…is used).
Regarding claim 2, Suzuki discloses the limitations of claim 1, and further:
wherein the operation includes an operation of reading information related to the plurality of memory blocks from the nonvolatile memory device ([0074]).
Regarding claim 3, Suzuki discloses the limitations of claim 2, and further:
wherein the information related to the plurality of memory blocks includes at least one of a read count, an erase count, the number of bit errors, a failed bit count, or any combination thereof ([0071]).
Regarding claim 4, Suzuki discloses the limitations of claim 1, and further:
wherein the result of the operation includes information indicating necessity or urgency of performing the refresh operation for the nonvolatile memory device ([0078]: the memory system according to this embodiment executes the overwrite refreshing when the number of error bits is the threshold Th2 or more and less than the threshold Th1 and executes the normal refreshing when the number of error bits is the threshold Th1).
Regarding claim 5, Suzuki discloses the limitations of claim 1, and further:
wherein the result of the operation includes status information comparing information related to the plurality of memory blocks acquired by the operation with a threshold value ([0075]: The refresh control unit 24 compares the calculated number of error bits of the block with a threshold Th1 (Step S10) and, in a case where the number of error bits is the threshold Th1 or more (Step S10: Yes), executes normal refreshing for this block (Step S20)).
Regarding claim 6, Suzuki discloses the limitations of claim 1, and further:
wherein the refresh operation is an operation of recovering data stored in the plurality of memory blocks for which at least one of a read count, an erase count, the number of bit errors, a failed bit count, or any combination thereof exceeds a threshold value ([0068]: by executing a refreshing process in which data stored in a block, of which the number of error bits exceeds a certain threshold in the error correction process executed by the ECC unit 23, is written into another block, the number of error bits of each block occurring in the error correction process is suppressed to be a constant number or less. Hereinafter, refreshing for rewriting data of a refreshing source block into a refreshing destination block will be referred to as normal refreshing).
Regarding claim 7, Suzuki discloses the limitations of claim 1, and further:
wherein the refresh operation is an operation of transferring data stored in the plurality of memory blocks to other memory blocks ([0068]).
Regarding claim 8, Suzuki discloses the limitations of claim 1, and further:
wherein the processor controls the nonvolatile memory device to perform a self refresh scan operation on the plurality of memory blocks without receiving the refresh scan request from the host device ([0068] describes normal refreshing, which does not require control external to the memory; however, per [0069], the overwrite refresh operation does require involvement of the controller: In the overwrite refreshing, the error cell is specified, and the same data is overwritten into the specified error cell, in other words, reprogramming is executed. The error cell may be specified by either the NAND control unit 12 of the NAND 10 or the control unit 20 of the memory controller 5. In a case where the error cell is specified by the control unit 20, there is a method using the error correction process executed by the ECC unit 23 or distribution reading).
Regarding claim 9, Suzuki discloses the limitations of claim 8, and further:
wherein the memory interface transfers a self refresh command for performing a self refresh operation to the nonvolatile memory device based on a result of the self refresh scan operation ([0075]: The refresh control unit 24 compares the calculated number of error bits of the block with a threshold Th1 (Step S10) and, in a case where the number of error bits is the threshold Th1 or more (Step S10: Yes), executes normal refreshing for this block (Step S20). Also see Fig. 8, steps S10 and S20).
Independent claim 10 is nearly identical in claimed subject matter to independent claim 1 and is rejected for the same reasons as independent claim 1.
Regarding claim 11, Suzuki discloses the limitations of claim 10. Claim 11 recites substantially the same limitations as claim 2, and henceforth is rejected for the same reasons.
Regarding claim 12, Suzuki discloses the limitations of claim 11. Claim 12 recites exactly the same limitations as claim 3, and henceforth is rejected for the same reasons.
Regarding claim 13, Suzuki discloses the limitations of claim 10. Claim 13 recites exactly the same limitations as claim 4, and henceforth is rejected for the same reasons.
Regarding claim 14, Suzuki discloses the limitations of claim 10. Claim 14 recites limitations that are substantially the same as claims 4 and 5, and henceforth is rejected for the same reasons.
Regarding claim 15, Suzuki discloses the limitations of claim 10. Claim 15 recites substantially the same limitations as claim 6, and henceforth is rejected for the same reasons.
Regarding claim 16, Suzuki discloses the limitations of claim 10. Claim 16 recites substantially the same limitations as claim 7, and henceforth is rejected for the same reasons.
Independent claim 17 contains a first and second limitation that are substantially the same as the first and third limitations of claim 1 and therefore those limitations are rejected for the same reasons as independent claim 1. Further, through Suzuki:
wherein the controller acquires information on the plurality of memory blocks from the nonvolatile memory device, and supplies status information indicating a degree to which a refresh operation is required based on the status information ([0049]-[0050]: The block management unit 22 executes the management of blocks included in the NAND 10 by using the block management table…In the block management table, for example, the following block management information is managed. The number of times of erasing in units of blocks).
Regarding claim 18, Suzuki discloses the limitations of claim 17. Claim 18 recites substantially the same limitation as the first limitation of claim 1, and henceforth is rejected for the same reasons.
Regarding claim 19, Suzuki discloses the limitations of claim 17. Claim 19 recites substantially the same limitation as the fourth limitation of claim 1, aside from including "fail count" and lacking of "read count". Regardless, due to the ‘or’ in the claim limitation, claim 19 is rejected for same reasons as claim 1.
Regarding claim 20, Suzuki discloses the limitations of claim 17. Claim 20 recites substantially the same limitations as claim 8, and henceforth is rejected for the same reasons.
Regarding claim 21, Suzuki discloses the limitations of claim 17. Further:
a processor (24) configured to acquire information on the plurality of memory blocks from the nonvolatile memory device, and to provide the status information indicating the degree to which the refresh operation is required to the host device based on the information ([0071]: The refresh control unit 24 manages a parameter used for determining whether or not normal refreshing is executed and a parameter used for determining whether or not overwrite refreshing is executed).
Conclusion
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/E.R.A./Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824
5/2/2026
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