DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al (US Patent 10163680).
Regarding claim 1, Hu teaches a semiconductor device, comprising:
a semiconductor substrate of a first conductivity type comprising a first surface (Fig. 1A/B, 102, col 4, lines 40-46, p-type);
a first device region formed in the semiconductor substrate and having the first conductivity type (Fig. 1A, 101, col 5, lines1-21, p-type), wherein the first device region has a lateral extent that is less than a lateral extent of the first surface of the semiconductor substrate (Fig. 1A, lateral extent of area encircled by 182 with 101 at center is less than lateral extent of 102);
an isolation structure electrically separating the first device region from the semiconductor substrate, wherein the isolation structure comprises a buried layer doped with a second conductivity type that opposes the first conductivity type (Fig. 1B, 106, col 5, lines 64-65, n-type) and a first elongate sinker of the second conductivity type that extends from the first surface into the semiconductor substrate and that is in electrical contact with the buried layer (Fig. 1A/B, 182 extends from 102a into 102 and in electrical contact with 106, col 8, lines 30-32, n-type); and
a breakdown voltage influencing structure of the second conductivity type that is arranged in the semiconductor substrate and laterally adjacent the buried layer (Fig. 1A/B, breakdown voltage influencing structure including 106, 122, and 182, col 5 lines 53-65; note that in the instant application para 31 states that the breakdown influencing structure may comprise one or more of the buried regions, the second sinker, the first sinker structure with its distal ends and the third sinker structure).
Regarding claim 2, Hu teaches the limitations of claim 1 upon which claim 2 depends.
Hu teaches wherein the breakdown voltage influencing structure comprises a second sinker of the second conductivity type that extends from the first surface into the semiconductor substrate and is arranged laterally adjacent the buried layer (Fig. 1A/B, 122 extending from 102a into 102 and laterally adjacent to 106, col 5, lines 64-65, n-type).
Regarding claim 3, Hu teaches the limitations of claim 2 upon which claim 3 depends.
Hu teaches wherein the breakdown voltage influencing structure comprises at least one buried region of the second conductivity type that is arranged laterally adjacent the buried layer (Fig. 1A and 3, 178 can be considered part of the breakdown influencing structure and is laterally adjacent to 106, col 7, lines 61-66 and col 8, lines 1-20).
Regarding claim 4, Hu teaches the limitations of claim 3 upon which claim 4 depends.
Hu teaches wherein the buried layer has a polygonal form in plan view with at least three corners (Fig. 1A/B, 106 polygon with at least 3 corners), and wherein one of the buried regions is arranged laterally adjacent one of the corners of the buried layer (Fig. 1A and 3, 178 laterally adjacent to one of the corners of 106).
Regarding claim 5, Hu teaches the limitations of claim 3 upon which claim 5 depends.
Hu teaches wherein the buried region overlaps the second sinker (Fig. 3, 178 overlaps 122).
Regarding claim 6, Hu teaches the limitations of claim 2 upon which claim 6 depends.
Hu teaches wherein the second sinker comprises a trench extending form the first surface into the semiconductor substrate and filled or lined with material of the second conductivity type, or comprises a doped region of the semiconductor substrate that is doped with dopants of the second conductivity type (Fig. 1B, 122 with trench 114, col 5, lines 64-65, n-type).
Regarding claim 7, Hu teaches the limitations of claim 1 upon which claim 7 depends.
Hu teaches wherein a first section of the first elongate sinker overlaps the buried layer and a second section of the first elongate sinker is arranged laterally adjacent the buried layer (Fig. 1A/B, sections of 182 overlap and laterally adjacent to 106), and wherein the second section provides the breakdown voltage influencing structure (col 3, lines 5-21, col 9, lines 8-20).
Regarding claim 8, Hu teaches the limitations of claim 7 upon which claim 8 depends.
Hu teaches wherein the buried layer has a polygonal form in plan view with at least three corners and the second section of the first elongate sinker is arranged laterally adjacent at least one of the corners (Fig. 1A/B, 106 polygonal form with at least 3 corners and section of 182 laterally adjacent to one of the corners).
Regarding claim 9, Hu teaches the limitations of claim 8 upon which claim 9 depends.
Hu teaches further comprising an additional elongate sinker that extends from the first surface to the buried layer and is in electrical contact with the buried layer (Fig. 1A/B, 122 extends from 102a to and in electrical contact with 106).
Regarding claim 10, Hu teaches the limitations of claim 9 upon which claim 10 depends.
Hu teaches wherein the second section of the first elongate sinker forms a central section of the first elongate sinker that is arranged laterally adjacent the buried layer, and wherein the first section of the elongate sinker comprises two distal end sections that overlap the buried layer (Fig. 1A/B, first sinker 182 adjacent to buried layer 106 with 2 distal end sections that overlap 106).
Regarding claim 11, Hu teaches the limitations of claim 10 upon which claim 11 depends.
Hu teaches wherein an end face of the distal end sections is substantially perpendicular to the additional elongate sinker, or the distal end sections have an outermost section that extends substantially parallel to the additional elongate sinker (Fig. 1A/B, first sinker 182 distal end sections perpendicular to second sinker 122).
Regarding claim 12, Hu teaches the limitations of claim 9 upon which claim 12 depends.
Hu teaches wherein the additional elongate sinker comprises a trench extending form the first surface into the semiconductor substrate and filled or lined with material of the second conductivity type, or comprises a doped region of the semiconductor substrate that is doped with dopants of the second conductivity type (Fig. 1B, 122 with trench 114, col 5, lines 64-65, n-type).
Regarding claim 13, Hu teaches the limitations of claim 1 upon which claim 13 depends.
Hu teaches wherein breakdown voltage influencing structure has a continuous ring form and laterally surrounds the first device region (Fig. 1A/B, breakdown voltage influencing structure including 174 and 114 has continuous ring laterally surrounding device region 101).
Regarding claim 14, Hu teaches the limitations of claim 1 upon which claim 14 depends.
Hu teaches wherein the first elongate sinker has a continuous ring form and laterally surrounds the first device region (Fig. 1A/B, 182 has continuous ring laterally surrounding device region 101).
Regarding claim 15, Hu teaches the limitations of claim 1 upon which claim 15 depends.
Hu teaches wherein the first elongate sinker comprises a trench extending form the first surface into the semiconductor substrate and filled or lined with material of the second conductivity type, or comprises a doped region of the semiconductor substrate that is doped with dopants of the second conductivity type (Fig. 1A/B, 182 with trench 174, col 8, lines 21-32).
Regarding claim 16, Hu teaches the limitations of claim 1 upon which claim 16 depends.
Hu teaches wherein the buried layer has a doping profile with tail regions and the breakdown voltage influencing structure has a doping profile with tail regions, wherein the tail regions of the buried layer overlap with the tail regions of the breakdown voltage influencing structure in regions in which the breakdown influencing structure is arranged laterally adjacent the buried layer and/or a maximum region of the breakdown voltage influencing structure overlaps a maximum region of the buried layer in regions in which the breakdown voltage influencing structure is in electrical contact with the buried layer (Fig. 1A/B, 106, 122, 182, Fig. 5A-C doping profile, col 15, lines 33-50).
Regarding claim 17, Hu teaches the limitations of claim 1 upon which claim 17 depends.
Hu teaches a first semiconductor device arranged in the first device region (Fig. 1A/B, device region 101 includes devices such as transistors, col 4 line 65 thru col 5 line 21); and
a second semiconductor device arranged in the semiconductor substrate (Fig. 1A/B, 190, col 4 line 65 thru col 5 line 21),
wherein the first semiconductor device is a gate driver for a high side switch of a half bridge circuit and the second semiconductor device is a gate driver for a low side switch of a half bridge circuit, or the first semiconductor device is a logic device and the second semiconductor device is a power device (Fig. 1A, 101 and 190, col 4 line 65 thru col 5 line 21, 101 low voltage logic and 190 high voltage power device).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Yilmaz (US Publication 20060076629) – Semiconductor devices with isolation and sinker regions containing trenches filled with conductive material.
Chan (US Patent 10074716) – Saucer-shaped isolation structures for semiconductor devices
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
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/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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