Prosecution Insights
Last updated: May 29, 2026
Application No. 18/510,815

SEMICONDUCTOR PACKAGE ASSEMBLY

Non-Final OA §102§103§112
Filed
Nov 16, 2023
Priority
Dec 08, 2022 — provisional 63/386,513
Examiner
HALL, VICTORIA KATHLEEN
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
MediaTek Inc.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
687 granted / 821 resolved
+15.7% vs TC avg
Strong +19% interview lift
Without
With
+19.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
21 currently pending
Career history
852
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
64.3%
+24.3% vs TC avg
§102
4.5%
-35.5% vs TC avg
§112
18.5%
-21.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 821 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification The disclosure is objected to because of the following informalities: Page 11, paragraph 27, line 6: Change 222 to 322. Compare with line 1 of the same paragraph. Page 18, paragraph 38, lien 5: Delete the second “240G,” at the end of the line. Page 18, paragraph 38, line 6: Add “is” before “disposed”. Page 20, paragraph 40, line 1 of the page: Delete the second “240G,”. Page 20, paragraph 41, line 5: Delete the second “240G,”. Page 21, paragraph 42, line 2 of the page: It appears that a word is missing in “includes a of”. Perhaps the word is “top surface”. Compare with line 3. Appropriate correction is required. Claim Objections Claims 13 and 15 are objected to because of the following informalities: Claim 13, line 3: Change “the letter X” to “a letter X” to provide antecedent basis. Claim 15, lines 1-2: Please provide antecedent basis for the two instances of “the thickness”. Antecedent basis has not been provided for either one. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 13 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 13, which depends from claim 9, which depends from claim 5, which depends from claim 4, which depends from claim 1: Claim 13 refers to “the letter X”. However, antecedent basis has not been provided for “the letter X”. Because antecedent basis has not been provided, claim 13 is rejected as indefinite. Regarding claim 15, which depends from claim 9, which depends from claim 5, which depends from claim 4, which depends from claim 1: Claim 15 refers to “the thickness” in two places, but no antecedent basis has been provided for these thicknesses. Because antecedent basis has not been provided, claim 15 is rejected as indefinite. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 and 16 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ogawa, U.S. Pat. Pub. No. 2005/0258548, Figure 12 or Figure 13. PNG media_image1.png 394 671 media_image1.png Greyscale PNG media_image2.png 363 680 media_image2.png Greyscale Regarding claim 1: Ogawa Figure 12 discloses a semiconductor package assembly (800), comprising: a base (110, 120, 140, 150, 160) having a top surface (120A) and a bottom surface (120B); a semiconductor package (820) disposed on the top surface (120A) of the base (110, 120, 140, 150, 160); and a capacitor (130) disposed on the semiconductor package (820) and located between the semiconductor package (820) and the base (110, 120, 140, 150, 160), wherein the capacitor (130) has a back surface (130B) located away from the semiconductor package (820), and wherein the back surface (130B) of the capacitor (130) is higher than the bottom surface (120B) of the base (110, 120, 140, 150, 160) and lower than the top surface (120A) of the base (110, 120, 140, 150, 160). Ogawa specification ¶¶ 181-186, 108-136. Similarly, Ogawa Figure 13 discloses a semiconductor package assembly, comprising: a base (320, 340, 351, 352, 353, 361, 362, 363) having a top surface (320A) and a bottom surface (320B); a semiconductor package (840) disposed on the top surface (320A) of the base (320, 340, 351, 352, 353, 361, 362, 363); and a capacitor (330) disposed on the semiconductor package (840) and located between the semiconductor package (840) and the base (320, 340, 351, 352, 353, 361, 362, 363), wherein the capacitor (330) has a back surface (unnumbered) located away from the semiconductor package (840), and wherein the back surface (unnumbered) of the capacitor (330) is higher than the bottom surface (320B) of the base (320, 340, 351, 352, 353, 361, 362, 363) and lower than the top surface (120A) of the base (320, 340, 351, 352, 353, 361, 362, 363). Id. ¶¶ 181-186, 162-167. Regarding claim 16: Ogawa Figure 12 discloses a semiconductor package assembly (800), comprising: a base (110, 120, 140, 150, 160) having a top surface (120A); a semiconductor package (820) disposed on the top surface of the base (110, 120, 140, 150, 160) by conductive structures (151), wherein the conductive structures (151) are connected between the top surface (120A) of the base (110, 120, 140, 150, 160) and the semiconductor package (820); and a capacitor (130) disposed on the semiconductor package (820) and surrounded by the conductive structures (151), wherein the capacitor (130) partially overlaps the base (110, 120, 140, 150, 160) in a direction substantially parallel with the top surface (120A) of the base (110, 120, 140, 150, 160). Id. ¶¶ 181-186, 108-136. Ogawa Figure 13 discloses a semiconductor package assembly, comprising: a base (320, 340, 351, 352, 353, 361, 362, 363) having a top surface; a semiconductor package (840) disposed on the top surface (320A) of the base (320, 340, 351, 352, 353, 361, 362, 363) by conductive structures (354), wherein the conductive structures (354) are connected between the top surface (320A) of the base (320, 340, 351, 352, 353, 361, 362, 363) and the semiconductor package (840); and a capacitor (330) disposed on the semiconductor package (840) and surrounded by the conductive structures (354), wherein the capacitor (330) partially overlaps the base (320, 340, 351, 352, 353, 361, 362, 363) in a direction substantially parallel with the top surface of the base (320, 340, 351, 352, 353, 361, 362, 363). Id. ¶¶ 181-186, 162-167. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa. Regarding claim 2, which depends from claim 1: Ogawa Figure 13 discloses first contact pads and second contact pads disposed on the semiconductor package (840) and close to the base (320, 340, 351, 352, 353, 361, 362, 363); and conductive structures (304) disposed on the first contact pads and electrically connected between the semiconductor package (840) and the base (320, 340, 351, 352, 353, 361, 362, 363), wherein the capacitor (330) is disposed on the second contact pads and surrounded by the conductive structures (304). Id. ¶¶ 181-186, 162-167, 24, 32. Regarding claim 3, which depends from claim 2: Ogawa discloses a first height of the capacitor (330) is greater than a second height of the conductive structures (304). See Ogawa Figure 13. Allowable Subject Matter Claims 4-12, 14, and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 13 and 15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims, and if the claim objections were addressed. The following is a statement of reasons for the indication of allowable subject matter: Arrangements in which capacitors are embedded substrates are well known in the art. See, e.g., Chiu, U.S. Pat. Pub. No. 2016/0071780, Figure 3; Hwang, U.S. Pat. Pub. No. 2018/0350747, Figure 9; Kanbe, U.S. Pat. Pub. No. 2020/0111732, Figure 1. Providing an opening in solder resist for an electronic component, specifically, a bridge chip, is also known. See, e.g., Gamba, U.S. Pat. Pub. No. 2021/0391266, Figure 2. However, the claims require “a capacitor disposed on the semiconductor package and located between the semiconductor package and the base, wherein the capacitor has a back surface located away from the semiconductor package, and wherein the back surface of the capacitor is higher than the bottom surface of the base and lower than the top surface of the base” (claim 1) and “the conductive structures are connected between the top surface of the base and the semiconductor package; and a capacitor disposed on the semiconductor package and surrounded by the conductive structures, wherein the capacitor partially overlaps the base in a direction substantially parallel with the top surface of the base” (claim 16). These limitations place specific requirements on the arrangement of the capacitor with respect to the semiconductor package and base, which limit suitable art for use in combining with the art used in the rejections. Because art suitable for combining the with primary reference was not identified during the search, claims 4 and 17 are allowable. With regard to claim 4: The claim has been found allowable because the prior art of record does not disclose “a first conductive layer disposed on the top surface of the build-up layer structure, a first solder mask layer disposed on the first conductive layer, wherein the top surface of the base is a top surface of the first solder mask layer, and wherein the first solder mask layer has a first opening for accommodate at least a portion of the capacitor”, in combination with the remaining limitations of the claim. With regard to claims 5-15: The claims have been found allowable due to their dependency from claim 4 above. With regard to claim 17: The claim has been found allowable because the prior art of record does not disclose “a first conductive layer disposed on the top surface of the build-up layer structure; and a first solder mask layer disposed on the first conductive layer, wherein the first solder mask layer has a first opening for accommodate at least a portion of the capacitor, and wherein the capacitor partially overlaps the first solder mask layer of the base in the direction substantially parallel with the top surface of the base”, in combination with the remaining limitations of the claim. With regard to claims 18-20: The claims have been found allowable due to their dependency from claim 17 above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTORIA KATHLEEN HALL whose telephone number is (571)270-7567. The examiner can normally be reached Monday-Friday, 8 a.m.-5 p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Victoria K. Hall/Primary Examiner, Art Unit 2897
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Prosecution Timeline

Nov 16, 2023
Application Filed
Mar 31, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+19.1%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 821 resolved cases by this examiner. Grant probability derived from career allowance rate.

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