DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta (U.S. PGPub 2023/0335464) in view of Bisi (U.S. PGPub 2024/0421139).
Regarding claim 1, Gupta teaches a microelectronic device comprising a first field effect transistor comprising a first active layer as well as a first drain, a first source, a first gate surmounting the active layer (Figs. 4F-4G, active layer 13, [0054]; drain 22, source 21, gate 23, [0054]),
a first rear electrode, underlying the first active layer in a stack direction (Z) perpendicular to a transverse plane (XY) defined by a first direction (X) and a second direction (Y), the first rear electrode being electrically connected to the first source (rear electrode 29, [0063]-[0066]),
a second field effect transistor comprising a second active layer as well as a second drain, a second source and a second gate surmounting the second active layer, the second source being electrically connected to the first drain, a second rear electrode, underlying the second active layer in the stack direction (Z), the second rear electrode being separated from the first rear electrode, the second rear electrode being electrically connected to the second source (Fig. 10, [0085], half-bridge circuit comprising two transistors each the same as Figs. 4F-4G, [0095]),
a stack ([0112]-[0119], half bridge circuit of Fig. 10 integrated, see Figs. 17C-D), wherein the stack comprises:
a continuous and GaN-based third active layer, underlying the first active layer, on the one hand, and underlying the second active layer ([0054], III-N structure comprises buffer, channel, and barrier layers, 2DEG formed between channel and barrier layers; isolation region 750 through the 2DEG, [0113], forming separated first/second active layers corresponding to the channel layer and leaving a continuous active layer below corresponding to the barrier and/or buffer layer),
and an insulating layer extending, in the stack direction (Z), between the first rear electrode and the first active layer, and between the second rear electrode and the second active layer, the insulating layer being continuous and with the basis of a first dielectric (Fig. 4G, insulating substrate 12, [0063]; [0113], single common insulating substrate 12, see Figs. 17C-D; [0054], insulating substrate 12 is sapphire).
Gupta does not explicitly teach the insulating layer having, in the stack direction (Z), a critical field Ec, the insulating layer having, in the stack direction (Z), a thickness called dielectric thickness e1500 of between 2*e1500,min and 10*e1500,min, with e1500,min=Vtarget/Ec, Vtarget being a target breakdown voltage of the insulating layer, the first dielectric having a heat conductivity λ1 greater than 1 W·m−1·K−1.
Gupta teaches wherein the insulating layer is sapphire ([0054]) and wherein the thickness is less than 200 μm ([0108]).
Regarding the heat conductivity, Claim 6 and the Specification state that the first dielectric may be sapphire. Where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. See MPEP 2112.01.
Bisi teaches a half bridge circuit integrated on an insulating substrate (Fig. 6A, [0064], sapphire), where the transistors may comprise rear electrodes (Fig. 2A, 225a/235a, [0042]), wherein the insulating substrate has a thickness of 50-100 μm ([0051]). Applicant’s Specification teaches where the first dielectric may be sapphire and wherein the e1500,min for sapphire may be 1-10 μm (Table), leading to a calculated e1500 of 2-100 μm. In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists. See MPEP 2144.05.
Alternatively, Bisi further teaches wherein the thickness of the insulating substrate is a result-effective variable which is optimized to control thermal resistance and breakdown voltage ([0051]). Mere optimization of a result-effective variable is prima facie obvious. See MPEP 2144.05IIB.
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Bisi with Gupta such that the insulating layer has a thickness satisfying the required formula because Bisi teaches that a thickness of 50-100 μm provides a high breakdown voltage ([0051], Claim 3) and/or to optimize the thickness of the insulating layer to control thermal resistance and breakdown voltage (Bisi, [0051]).
Regarding claim 2, the combination of Gupta and Bisi teaches wherein Vtarget≥900V (Bisi, Claim 3; Gupta, [0009], [0017]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Gupta and Bisi for the reasons set forth in the rejection of claim 1.
Regarding claim 3, the combination of Gupta and Bisi does not explicitly teach wherein, in the transverse plane (XY), the first rear electrode and the second rear electrode are separated by a lateral insulation distance dins greater than 50 μm.
Gupta teaches wherein rear electrodes are separated by a lateral insulation distance greater than 10 μm ([0060]), and wherein electrode separation distance must be sufficient to prevent arcing and short circuits ([0071]) while maintaining reduced device size ([0058]). Therefore, electrode separation distance is a result-effective variable. Mere optimization of a result-effective variable is prima facie obvious. See MPEP 2144.05IIB.
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to further combine the teachings of Gupta and Bisi such that the first rear electrode and the second rear electrode are separated by a lateral insulation distance dins greater than 50 μm for the purpose of optimizing the rear electrode separation distance (Gupta, [0058], [0071]).
Regarding claim 4, the combination of Gupta and Bisi teaches wherein, projecting in the transverse plane (XY) and in any direction of the transverse plane (XY): the first rear electrode projects with respect to the first active layer over a first overflow distance dover,1, with dover,1>0, and the second rear electrode projects with respect to the second active layer over a second overflow distance dover,2, with dover,2>0 (Gupta, [0120]-[0121] the device may comprise a DBC configured similar to Figs. 12A-12B; Fig. 12B, rear electrode is output plate 222 connected to source via 17, [0097]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Gupta and Bisi for the purpose of providing a base substrate for the module with reduced size (Gupta, [0096], [0120]).
Regarding claim 5, the combination of Gupta and Bisi teaches wherein the stack has a thickness e1000 in the vertical direction (substrate + active layer) but does not explicitly teach wherein dover,1≥e1000 and dover,2≥e1000.
The examiner takes official notice that a conductor formed as part of a DBC substrate, as taught by Gupta, is commonly greater than 200um, and the active layer stack on a GaN-based HEMT device is commonly 10um or less. Therefore it would have been obvious to a person having ordinary skill in the art to modify the teachings of Gupta and Bisi such that dover,1≥e1000 and dover,2≥e1000 for the reasons set forth in the rejection of claim 4.
Regarding claim 6, the combination of Gupta and Bisi teaches wherein the first dielectric is sapphire (Gupta, [0054]; Bisi, [0064]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Gupta and Bisi for the reasons set forth in the rejection of claim 1.
Regarding claim 7, the combination of Gupta and Bisi teaches a first electrical connection element passing through the stack and electrically connecting the first source to the first rear electrode (Gupta, Fig. 4G, 17, [0066]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Gupta and Bisi for the reasons set forth in the rejection of claim 1.
Regarding claim 8, the combination of Gupta and Bisi teaches a second electrical connection element passing through the stack and electrically connecting the second source to the second rear electrode (Gupta, Fig. 4G, 17, [0066]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Gupta and Bisi for the reasons set forth in the rejection of claim 1.
Regarding claim 9, the combination of Gupta and Bisi teaches wherein e1500≥1 μm (Gupta, [0108]; Bisi, [0051]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Gupta and Bisi for the reasons set forth in the rejection of claim 1.
Regarding claim 10, the combination of Gupta and Bisi teaches wherein the third active layer is directly in contact with the first active layer and with the second active layer (Gupta, [0054], the III-N layers form a single material structure; see rejection of claim 1). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Gupta and Bisi for the reasons set forth in the rejection of claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALIA SABUR whose telephone number is (571)270-7219. The examiner can normally be reached M-F 9:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALIA SABUR/Primary Examiner, Art Unit 2812
Prosecution Insights