DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/16/2023 was filed after the mailing date of the non-final action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
Claim 17 recites the limitation " forming a second mask layer at a central of the initial second conductive bump, wherein the second mask layer comprises at least one concave surface; and removing part not covered by the second mask layer of the initial second conductive bump by etching to form the second conductive structure." In last 5 lines of claim 17. There is insufficient antecedent basis for this limitation in the claim.
Claim 17 depends on claim 16, which depends on claim 15 and claim 15 depends on claim 13. Claim 13 does not mention a first mask layer therefore it is unclear if the applicant meant for claim 17 to depend on claim 14 instead or if the instead the claim was meant to read “a mask layer at a central of the initial second conductive bump, wherein the mask layer comprises at least one concave surface; and removing part not covered by the mask layer of the initial second conductive bump by etching to form the second conductive structure.”
For purposes of examination the claim limitation will be interpreted as any mask layer part of a secondary bump structure of the device.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-13 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wakioka (US 2021/0074657 A1).
Regarding claim 1: Wakioka teaches a semiconductor structure (fig.3,4 and 8 and 12), comprising:
a substrate (120);
and a chip stack (C1-C3) disposed on the substrate (120) through a plurality of first conductive structures (30,51,52 and 60 on left side hereinafter LCS);
wherein each of the plurality of the first conductive structures (100) comprises a first conductive bump (60 and 52 of LCS hereinafter CB) comprising at least one concave surface (recessed portion P1), and concave surfaces (P1) of adjacent first conductive bumps (CB) are disposed (as shown in fig.4) facing each other.
Regarding claim 2: Wakioka teaches the semiconductor structure of claim 1, wherein a plurality of the first conductive structures (LCS) are in a quadrilateral arrangement (as shown in fig.4), and for the plurality of the first conductive structures (LCS) in the quadrilateral arrangement, the concave surfaces (P1) of the first conductive bumps (CB) of the first conductive structures (LCS) at diagonal positions (as shown in fig.4 and 12) are disposed facing each other.
Regarding claim 3: Wakioka teaches the semiconductor structure of claim 2, wherein,
a distance from a diagonal intersection point of the quadrilateral arrangement to the concave surface (P1) of each of the first conductive bumps (CB) is defined as a first distance (DST2b or DST2a from intersecting center hereinafter D1);
a distance from the concave surface (P1) of each of the first conductive bumps (CB) to a center of the first conductive bump (CB) is defined as a second distance (D11a from center origin hereinafter D2 as shown in fig. 4);
and a ratio (as shown in fig. 4 or 12) of the first distance (D1) to the second distance (D2) ranges (as shown in fig. below) from 5: 3 to 5: 2.
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Regarding claim 4: Wakioka teaches the semiconductor structure of claim 2, wherein, the first conductive bump (CB) further comprises at least one convex surface (P2) arranged adjacent to the concave surface (P1).
Regarding claim 5: Wakioka teaches the semiconductor structure according to claim 4, wherein, each of the first conductive bumps (CB) comprises a plurality of concave surfaces (P1);
a convex surface (P2) is arranged between two adjacent ones of the plurality of the concave surfaces (P1);
and an area of each of the concave surfaces (P1) is larger (as shown in fig.4) than an area of the convex surface (P2).
Regarding claim 6: Wakioka teaches the semiconductor structure of claim 1, wherein, each of the plurality of the first conductive structures (LCS) further comprises (fig.8) a first through silicon via (30 can be a silicon via par. 24) disposed on the first conductive bump (CB) and a first test pad (32) disposed between the first through silicon via (30) and the first conductive bump (CB).
Regarding claim 7: Wakioka teaches the semiconductor structure of claim 1, wherein, the first conductive bump (CB) comprises a first solder ball (60) and a first solder pad (56) disposed on the first solder ball (60);
wherein an orthographic projection of the first solder pad (56) on the substrate (120) is in an orthographic projection of the first solder ball (60) on the substrate (120).
Regarding claim 8: Wakioka teaches the semiconductor structure of claim 7, wherein, the first solder pad (56) comprises (fig.8) a first sub-solder pad (56a of fig. below) and a second sub-solder pad (56b of fig. below), the first sub-solder pad (56a) being disposed on the second sub-solder pad (56b);
wherein a volume of the first sub-solder pad (56a) is smaller than a volume of the second sub-solder pad (56b).
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Regarding claim 9: Wakioka teaches the semiconductor structure of claim 6, wherein, the chip stack (C1-C3) comprises a plurality of chips (C1, C2, or C3) sequentially stacked, each of the plurality of the chips (C1, C2, or C3) comprises n (2) first conductive structures (LCS), n being greater than or equal to 2;
projections of first through silicon vias (30) of corresponding first conductive structures (LCS) in two adjacent layers of the chips (C1, C2 or C3) are non-overlapping (as shown in fig.3) in a projection along a direction perpendicular to a plane of the substrate (120).
Regarding claim 10: Wakioka teaches the semiconductor structure of claim 2, wherein the semiconductor structure (fig.3) further comprises: a second conductive structure (30,51,52 and 60 on right side hereinafter RCS), disposed at a diagonal intersection point of the quadrilateral arrangement, and comprising a second conductive bump (60 and 52 of RCS hereinafter CB2); wherein the second conductive bump (CB2) comprises at least one concave surface (P1 of CB2).
Regarding claim 11: Wakioka teaches the semiconductor structure of claim 10, wherein, each concave surface (P1 of CB2) of the second conductive bump (CB2) is disposed (as shown in fig.12) facing one concave surface (P1 of CB) of the first conductive bump (CB) adjacent to the second conductive bump (CB2).
Regarding claim 12: Wakioka teaches the semiconductor structure of claim 10, wherein, each of the plurality of the first conductive structures (LCS) is a signal conductive structure, and the second conductive structure (RCS) is a grounded conductive structure. The claimed and prior art products of Wakioka are structurally the same (as shown in fig.3) therefore the first and second conductive structures (LCS and RCS respectively) would have the same property of being able to be used as signal/ground. Also, the conductive structures of the prior art product and the claimed art are structurally the same so they could function as signal ground. (See MPEP 2112.01(i) and 2114).
Regarding claim 13: Wakioka teaches (figs. 3-4,8 and 12) a method for manufacturing a semiconductor structure (fig.3), comprising:
Providing (par.30) a substrate (120);
and forming (par.30, fig.2) a chip stack (C1-C3), wherein on the chip stack (C1-C3), a plurality of first conductive structures (30,51,52 and 60 on left side hereinafter LCS) are formed, the chip stack (C1-C3) is disposed on the substrate (120) through the plurality of the first conductive structures (LCS);
wherein, each of the plurality of the first conductive structures (LCS) comprises (figs.3-4, par. 31-33) a first conductive bump (60 and 52 of LCS hereinafter CB) comprising at least one concave surface (P1 of CB), and concave surfaces (P1) of adjacent first conductive bumps (CB) are disposed facing each other (as shown in fig.4 and 12).
Regarding claim 15: The method of claim 13, wherein, a plurality of the first conductive structures (LCS) are in a quadrilateral arrangement (as shown in fig. 4 and 12), and for the plurality of the first conductive structures (LCS) in the quadrilateral arrangement, the concave surfaces (P1) of the first conductive bumps (CB) of the first conductive structures (LCS) at diagonal positions are disposed (as shown in fig. 4 and 12) facing each other.
Regarding claim 16: The method of claim 15, further comprising:
Forming (par.24-32, figs. 1-3) a second conductive structure (30,51,52 and 60 on right side hereinafter RCS) at a diagonal intersection point of each quadrilateral arrangement (as shown in figs. 4 and 12), wherein the second conductive structure (LCS) comprises a second conductive bump (60 and 52 of RCS hereinafter CB2) comprising at least one concave surface (P1 of CB2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Wakioka (US 20210074657 A1) as applied to claim 13 above and in further view of Topacio (US 20130256871 A1)
Regarding claim 14: Wakioka teaches the method of claim 13, wherein, the step of forming a plurality of the first conductive structures (LCS) comprises:
forming (figs.2-3) initial first conductive structures (LCS), wherein each of the initial first conductive structures (LCS) comprise an initial first conductive bump (CB) of a circular shape (as shown in fig3);
Wakioka is silent to explicitly teaching forming at least one first mask layer on each of the initial first conductive bumps, wherein the first mask layer covers part of a periphery of the initial first conductive bump;
and removing part covered by the first mask layer of the initial first conductive bumps by etching to form the plurality of the first conductive structure.
Topacio teaches (fig.9 and 11) forming (fig.9, par.40-41) at least one first mask layer (194) on each of the initial first conductive bumps (35), wherein the first mask layer (194) covers part of a periphery (area of 197) of the initial first conductive bump (35);
and removing (par.40) part covered by the first mask layer (194) of the initial first conductive bumps (35) by etching to form the plurality of the first conductive structure (35,80, 50a-d hereinafter 1CS).
It would have been obvious to one of ordinary skill in the art before the effecting filing date of the claimed invention to include the lithography and etching technique of Topacio that includes a mask layer towards the formation of the conductive bump of Wakioka in order to have the predictable result of better precision, reliability, accuracy during manufacturing of the conductive bump CB of Wakioka to better achieve the design spec requirements of the conductive bump, prevent solder bridging, and ultimately improve consistency.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Wakioka (US 20210074657 A1) as applied to claim 16 above and in further view of Topacio (US 20130256871 A1)
Regarding claim 17: The method of claim 16, wherein the step of forming a second conductive structure (RCS) comprises:
forming an initial second conductive structure (RCS) at the diagonal intersection point of the quadrilateral arrangement (as shown in figs. 4 and 12), wherein the initial second conductive structure (RCS) comprises an initial second conductive bump (CB2) of a circular shape (as shown in fig. 3);
Wakioka is silent to teach forming a second mask layer at a central of the initial second conductive bump, wherein the second mask layer comprises at least one concave surface;
and removing part not covered by the second mask layer of the initial second conductive bump by etching to form the second conductive structure.
Topacio teaches (fig.9 and 11) forming (fig.9 and 11, par.40-41) a second mask layer (second 194 corresponding to second bump 35) at a central of the initial second conductive bump (second bump 35/285a hereinafter 35-2), wherein the second mask layer (second 194) comprises at least one concave surface (296a-d);
and removing (par.40) part (197) not covered by the second mask layer (second mask layer of second bump 35-2) of the initial second conductive bump (35-2) by etching to form the second conductive structure (35,80, 50a-d hereinafter 1CS).
It would have been obvious to one of ordinary skill in the art before the effecting filing date of the claimed invention to include the lithography and etching technique of Topacio that includes a mask layer towards the formation of the conductive bump of Wakioka in order to have the predictable result of better precision, reliability, accuracy during manufacturing to better achieve the design spec of the conductive bump and prevent solder bridging and ultimately improve consistency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICKY VERDES whose telephone number is (703)756-1401. The examiner can normally be reached Monday - Friday 07:30 - 03:30 PM.
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/RICKY VERDES/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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