DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 16 Nov 2023 and 15 Nov 2024 have been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following titles are suggested:
“VERTICAL CHANNEL TRANSISTOR WITH CONDUCTIVE LINER STRUCTURE FOR CONTROLLING THRESHOLD VOLTAGE”; or
“VERTICAL CHANNEL TRANSISTOR WITH CONDUCTIVE LINER STRUCTURE”.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “first conductive patterns contacting the gate insulation layer and protruding beyond a sidewall of the gate structure” of claim 1 must be shown or the feature canceled from the claim.
Likewise, the “conductive liner structure protruding beyond a sidewall of the gate structure” of claim 8 must be shown or the feature canceled from the claim. No new matter should be entered.
Note that paragraph [0035] of the specification states: “As illustrated in FIG. 4, a top surface of the first conductive layer pattern 136a covering the third and fourth sidewalls of the first active pattern 108 may be higher than a top of the gate pattern 150, e.g., relative to the bottom of the substrate 100. The first conductive layer pattern 136a may protrude from (e.g., beyond) one sidewall of the gate structure G in the first direction X while contacting the gate insulation layer of the gate structure G (FIG. 1).”
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In claim 1, the examiner is uncertain if claim 1’s “first conductive patterns contacting the gate insulation layer and protruding beyond a sidewall of the gate structure” is referring to the portion of FIG. 4 that the examiner has circled above. The examiner finds it more likely that the quoted portion of claim 1 is an attempt to restate the subject matter of ¶[0035]. The examiner suggests the following modification to a portion of claim 1 to provide clear agreement between claim 1 and FIG. 4: “first conductive patterns contacting the gate insulation layer and protruding in a second direction, perpendicular to the first direction, from a sidewall of the gate structure”.
Likewise, the examiner suggests the following modification to a portion of claim 8 to provide clear agreement between claim 8 and FIG. 4: “a conductive liner structure protruding in the first direction from a sidewall of the gate structure”. (Note that in claim 8, X is the first direction and Y is the second direction in FIG. 4, whereas in claim 1, Y is the first direction.)
That is, FIG. 4 shows the following elements from claim 1: a gate structure G including a gate insulation layer 140 and a gate pattern 150 laterally stacked on a first sidewall of the first active pattern 108, the gate pattern 150 facing the first sidewall of the first active pattern 108 and extending in a first direction Y parallel to an upper surface of the substrate 100; and first conductive patterns 136a contacting the gate insulation layer 140 and protruding in a second direction X from a sidewall of the gate structure G, the first conductive patterns 136a facing second and third sidewalls in the first direction Y of the first active pattern 108, and the first conductive patterns 136a being spaced apart from the first active pattern 108.
Corrected drawing sheets will not be required if claim 1 and claim 8 are amended to be in clear agreement with FIG. 4.
Otherwise, corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 4 is objected to because of the following informality: in the third line, the second mention of “a bottom of the gate structure” should be changed to “the bottom of the gate structure”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3–7, 17, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation “the first conductive layer pattern” in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 3 depends on claim 1, which introduced “first conductive patterns”. For the purpose of examination, the examiner will interpret “the first conductive layer pattern” to refer to the “first conductive patterns” from claim 1.
Claim 4 recites the limitation “the first conductive layer patterns” in lines 4–5. There is insufficient antecedent basis for this limitation in the claim. Claim 4 depends on claim 1, which introduced “first conductive patterns”. For the purpose of examination, the examiner will interpret “the first conductive layer patterns” to refer to the “first conductive patterns” from claim 1.
Claim 5 recites the limitation “the first conductive layer patterns” in lines 1–2. There is insufficient antecedent basis for this limitation in the claim. Claim 5 depends on claim 1 (through claim 4), which introduced “first conductive patterns”. For the purpose of examination, the examiner will interpret “the first conductive layer patterns” to refer to the “first conductive patterns” from claim 1.
Claim 6 recites the limitation “the first conductive layer patterns” in line 1–2. There is insufficient antecedent basis for this limitation in the claim. Claim 6 depends on claim 1, which introduced “first conductive patterns”. For the purpose of examination, the examiner will interpret “the first conductive layer patterns” to refer to the “first conductive patterns” from claim 1.
Claim 7 recites the limitation “the first conductive layer patterns” twice in line 2 and in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 7 depends on claim 1, which introduced “first conductive patterns”. For the purpose of examination, the examiner will interpret “the first conductive layer patterns” to refer to the “first conductive patterns” from claim 1.
Claim 17 recites the limitation “The vertical semiconductor device as claimed in claim 8” in line 1. There is insufficient antecedent basis for this limitation in the claim. Claim 8 introduced “A semiconductor device”. For the purpose of examination, the examiner will interpret “The vertical semiconductor device as claimed in claim 8” to refer to the “semiconductor device” from claim 8.
Claim 20 recites the limitation “the first conductive liner structure” in lines 1–2. There is insufficient antecedent basis for this limitation in the claim. Claim 20 depends on claim 18, which introduced “a conductive liner structure”. For the purpose of examination, the examiner will interpret “the first conductive liner structure” to refer to the “conductive liner structure” from claim 18.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1–2 and 6 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by US 2012/0153365 A1 by Sung.
Regarding claim 1, Sung teaches:
A semiconductor device (FIG. 1), comprising:
a substrate 100 (“semiconductor substrate 100” including “a lower substrate 100b and an upper substrate 100a” ¶[0059]);
a first active pattern 105a (“pillar patterns 105a-d” ¶[0043]) protruding from the substrate 100;
a gate structure 240a (“first and second word lines 240a–b” ¶[0080]) including a gate insulation layer 135 (FIG. 2L(ii), “first gate insulating layer 135” ¶[0072]) and a gate pattern 240a laterally stacked on a first sidewall (in the Y1-Y1′ direction as shown in FIG. 2L(ii)) of the first active pattern 105a, the gate pattern 240a facing the first sidewall (in the Y1-Y1′ direction as shown in FIG. 1) of the first active pattern 105a and extending in a first direction (the X-X′ direction in FIG. 1) parallel to an upper surface of the substrate 100; and
first conductive patterns 140a+c (“first and the second gate patterns (140a, 140b)” ¶[0020], “third and fourth gate patterns (140c, 140d)” ¶[0021]) contacting the gate insulation layer 135 (as shown in FIG. 2L(i)) and protruding beyond a sidewall of the gate structure 240a (i.e., 140a protrudes in the Y2-Y2′ direction from a sidewall of the gate structure 240a as shown in FIG. 1), the first conductive patterns 140a+c facing second and third sidewalls in the first direction (the X-X′ direction in FIG. 1 and FIG. 2L(i)) of the first active pattern 105a, and the first conductive patterns 140a+c being spaced apart from the first active pattern 105a (by the intervening gate insulation layer 135).
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Regarding claim 2, Sung teaches:
The semiconductor device as claimed in claim 1, wherein a top surface of the gate structure 240a is lower than a top surface of the first active pattern 105a (as shown in FIGS. 1 and 2L(ii) ).
Regarding claim 6, Sung teaches:
The semiconductor device as claimed in claim 1, wherein the first conductive layer patterns [“first conductive patterns” from claim 1] 140a–c include titanium nitride or tungsten (“The gate material 140 may include a material such as titanium nitride, tungsten, or a combination thereof” ¶[0073]).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if rewritten to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action. The closest prior art of Sung, as applied to the rejection of claim 1 above, fails to teach that
“a top surface of the gate structure is lower than a top surface of the first conductive layer pattern1.”
That is, Sung’s FIG. 1 shows that the top surface of the gate structure 240a is at the same height as the top surface of the first conductive patterns 140a+c.
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if rewritten to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action. The closest prior art of Sung, as applied to the rejection of claim 1 above, fails to teach that there is
“a second conductive layer pattern spaced apart from a bottom of the gate structure, the second conductive layer pattern being under a bottom of the gate structure, and the second conductive layer pattern being electrically connected to lower portions of the first conductive layer patterns2.”
That is, Sung’s FIG. 1 shows that the top surface of the gate structure 240a is at the same height as the top surface of the first conductive patterns 140a+c.
Claim 5 is objected to as being dependent upon a rejected base claim (claim 1), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if rewritten to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action. Claim 5 would be allowable at least for the reason that claim 5 depends on claim 4, which contains allowable subject matter as described above.
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if rewritten to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action. The closest prior art of Sung, as applied to the rejection of claim 1 above, fails to teach that there is
“an insulation layer between the first conductive layer patterns3 and the first active pattern, the gate insulation layer being positioned between the first conductive layer patterns and the gate pattern.”
That is, FIG. 1 of the present application shows an insulation layer 106a between the first conductive patterns 136a and the first active pattern 108, the gate insulation layer 140 (FIG. 2) being positioned between the first conductive patterns 136a and the gate pattern 150 (as shown in FIG. 1). In other words, the present application requires that the first conductive patterns 136a and the gate pattern 150 are electrically isolated from each other so that the voltage of the first conductive patterns 136a and the voltage of the gate pattern 150 can be set independently to different voltages. Paragraph [0040] of the present application explains: “The conductive liner structure 136 may induce electric fields in the first active pattern 108 so that a threshold voltage of the vertical channel transistor may be controlled by inducing electric fields in the first active pattern 108.”
However, the closest prior art of Sung, as applied to the rejection of claim 1 above, teaches that the first conductive patterns 140a+c are electrically coupled to the gate pattern 240a (“A first word line (240a) coupled to the first and the third gate patterns (140a, 140c)” ¶[0022]), and thus Sung does not teach that the gate insulation layer 135 is positioned between the first conductive patterns 140a+c and the gate pattern 240a.
Claim 8 is allowed. The closest prior art of Sung, as applied to the rejection of claims 1–2 and 6 above, fails to teach
“a conductive liner structure protruding beyond [from] a sidewall of the gate structure, the conductive liner structure being spaced apart from the first active patterns, and the conductive liner structure facing each of third and fourth sidewalls in the second direction of the first active patterns,
wherein the conductive liner structure includes:
first conductive layer patterns facing the third and fourth sidewalls of each of the first active patterns, and being spaced apart from the first active patterns; and
a second conductive layer pattern electrically connected to lower portions of the first conductive layer patterns”
in combination with all other limitations in the claim as claimed and defined by applicant.
That is, FIG. 4 of the present application shows a second conductive layer pattern 136b electrically connected to lower portions of the first conductive layer patterns 136a.
However, Sung’s FIG. 1 does not include a second conductive layer pattern electrically connected to lower portions of the first conductive layer patterns 140a+c as required by claim 8.
Claims 9–16 are allowed at least for the reason that they depend on allowed claim 8.
Claim 17 would be allowable if rewritten or amended to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Claim 17 would be allowable at least for the reason that it depends on allowed claim 8.
Claim 18 is allowed. The closest prior art of Sung, as applied to the rejection of claims 1–2 and 6 above, fails to teach
“a conductive liner structure facing each of second and third sidewalls in the second direction of the first active patterns, the conductive liner structure being spaced apart from the gate pattern and the first active patterns”
in combination with all other limitations in the claim as claimed and defined by applicant.
The closest prior art of Sung teaches that the conductive liner structure 140a+c is electrically coupled to the gate pattern 240a (“A first word line (240a) coupled to the first and the third gate patterns (140a, 140c)” ¶[0022]), and thus Sung does not teach that the conductive liner structure 140a+c is spaced apart from the gate pattern 240a as required by claim 18, there being no indication by Sung that the gate insulation layer 135 is positioned between the conductive liner structure 140a+c and the gate pattern 240a so as to provide for physical separation and electrical isolation.
Claim 19 is allowed at least for the reason that it depends on allowed claim 18.
Claim 20 would be allowable if rewritten or amended to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Claim 20 would be allowable at least for the reason that it depends on allowed claim 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 7,355,230 B2 by Thies et al. (see FIG. 1A),
US 8,324,682 B2 by Chen et al. (see FIG. 2A),
US 2022/0302318 A1 by Ramaswamy et al. (see FIG. 1A), and
US 2022/0076732 A1 by Kang et al. (see FIG. 17)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam J Mott whose telephone number is (571)272-2367. The examiner can normally be reached Mon-Fri 8:30AM-5:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.J.M./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
1 Interpreted to refer to the “first conductive patterns” of claim 1; see rejection under 35 USC § 112(b) above.
2 Interpreted to refer to the “first conductive patterns” of claim 1; see rejection under 35 USC § 112(b) above.
3 Interpreted to refer to the “first conductive patterns” of claim 1; see rejection under 35 USC § 112(b) above.
Prosecution Insights