DETAILED ACTION
Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Election/Restrictions
Applicant’s election without traverse of Invention I (semiconductor device), species A/fig. 1-20, reflected in claims 1-14 and 19-20 in the reply filed on 03/30/2025 is acknowledged. Claims 15-18 are withdrawn from further consideration pursuant to 37 CFR 1.142 (b), as being drawn to the nonelected group.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore elements, ‘level of the top surface of the buffer insulating layer’ and ‘level of the top surface of the top electrode’ cited in claim 14, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
14. The semiconductor device of claim 11, wherein
…….
a level of the top surface of the buffer insulating layer is lower than the level of the top surface of the top electrode.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-14 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang; Hui-Lin et al. (US 20210167281 A1, hereinafter Wang'281).
Regarding independent claim 1, Wang'281 teaches, “A semiconductor device (fig. 1-12; ¶ [0010] - ¶ [0032]), comprising:
a substrate (fig. 12) including a cell region (14) and a peripheral region (16);
a bottom electrode (52) overlapping the cell region;
a magnetic tunnel junction pattern (36) on the bottom electrode;
a top electrode (54) on the magnetic tunnel junction pattern (36);
a buffer insulating layer (58) overlapping the peripheral region (16);
a capping insulating layer (74, 86, 62, 56) in contact with a side surface of the top electrode (54) and a top surface of the buffer insulating layer (58); and
a first peripheral conductive structure (82, 60) penetrating the capping insulating layer (74, 86, 62) and the buffer insulating layer (58), wherein
a level difference between the top surface of the buffer insulating layer (58) and a top surface of the top electrode (54) is smaller than a thickness of the capping insulating layer (74, 86, 62, 56).
Regarding claim 2, Wang'281 further teaches, “The semiconductor device of claim 1, further comprising:
a filling insulating layer (76) on the capping insulating layer (74, 86, 62), wherein
the filling insulating layer (76) comprises a filling insulating portion between the top electrode (54) and the buffer insulating layer (58), and
a dielectric constant of the buffer insulating layer (58, “an ultra low-k (ULK) dielectric layer such as porous dielectric materials including but not limited to for example silicon oxycarbide (SiOC)”, ¶ [0021]) is smaller than a dielectric constant of the filling insulating layer (76, silicon oxide, ¶ [0023]).
Regarding claim 4, Wang'281 further teaches, “The semiconductor device of claim 1, further comprising:
a bottom electrode contact (28) connected to the bottom electrode (34);
a lower insulating layer (26) enclosing the bottom electrode contact (28); and
a molding insulating layer (30, 32) between the lower insulating layer (26) and the buffer insulating layer (58).
Regarding claim 5, Wang'281 further teaches, “The semiconductor device of claim 4, wherein
the capping insulating layer (74, 86, 62, 56) comprises a first portion and a second portion,
the first portion of the capping insulating layer (74, 86, 62, 56) is in contact with the top surface of the buffer insulating layer (58), and
the second portion of the capping insulating layer (56) is in contact with a side surface of the buffer insulating layer (58) and a side surface of the molding insulating layer (30, 32)”.
Regarding claim 6, Wang'281 further teaches, “The semiconductor device of claim 4, further comprising:
an intervening insulating layer (32) between the molding insulating layer (30) and the buffer insulating layer (58), wherein
a dielectric constant of the intervening insulating layer (32) is higher than a dielectric constant of the buffer insulating layer (58) and a dielectric constant of the molding insulating layer (30) (choice of materials)”.
Regarding claim 7, Wang'281 further teaches, “The semiconductor device of claim 6, wherein the first peripheral conductive structure comprises a first peripheral contact portion (60) and a first peripheral line portion (20) on the first peripheral contact portion, and the first peripheral contact portion (60) penetrates the intervening insulating layer (32/22)”.
Regarding claim 8, Wang'281 further teaches, “The semiconductor device of claim 7, further comprising:
a second peripheral conductive structure (similar to 82, 60) penetrating the lower insulating layer (58) and the molding insulating layer (30, 32), wherein
the second peripheral conductive structure comprises a second peripheral contact portion (60) and a second peripheral line portion (20) on the second peripheral contact portion, and
a bottom surface of the intervening insulating layer (32) is in (indirect) contact with a top surface of the second peripheral line portion (20)”.
Regarding claim 9, Wang'281 further teaches, “The semiconductor device of claim 1, further comprising: a protection insulating layer (78) on the capping insulating layer (74, 86, 62, 56), wherein a dielectric constant of the capping insulating layer is smaller than a dielectric constant of the protection insulating layer (choice of materials)”.
Regarding claim 10, Wang'281 further teaches, “The semiconductor device of claim 9, wherein the first peripheral conductive structure (82, 62) penetrates the protection insulating layer (78)”.
Regarding independent claim 11, Wang'281 teaches, “A semiconductor device (fig. 1-12; ¶ [0010] - ¶ [0032]), comprising:
a substrate (fig. 12) including a cell region (14) and a peripheral region (16);
a bottom electrode (52) overlapping the cell region;
a magnetic tunnel junction pattern (36) on the bottom electrode;
a top electrode (54) on the magnetic tunnel junction pattern (36);
a buffer insulating layer (58) overlapping the peripheral region (16);
a capping insulating layer (74, 86, 62, 56) in contact with a side surface of the top electrode (54) and a top surface of the buffer insulating layer (58);
a filling insulating layer (76) on the capping insulating layer (74, 86, 62, 56); and
a first peripheral conductive structure (82, 60) penetrating the capping insulating layer (74, 86, 62) and the buffer insulating layer (58), wherein
the filling insulating layer (76, 56) includes a filling insulating portion disposed between the buffer insulating layer (58) and the top electrode (54), and
a dielectric constant of the buffer insulating layer (58, “an ultra low-k (ULK) dielectric layer such as porous dielectric materials including but not limited to for example silicon oxycarbide (SiOC)”, ¶ [0021]) is smaller than a dielectric constant of the filling insulating layer (76, silicon oxide, ¶ [0023]).
Regarding claim 12, Wang'281 further teaches, “The semiconductor device of claim 11, wherein a dielectric constant of the capping insulating layer (62, SiCN) is smaller than the dielectric constant of the filling insulating layer (76, silicon oxide)”.
Regarding claim 13, Wang'281 further teaches, “The semiconductor device of claim 11, wherein a thickness of the buffer insulating layer (58) is larger than a thickness of the capping insulating layer (74, 86, 62)”.
Regarding claim 14, Wang'281 further teaches, “The semiconductor device of claim 11, wherein
the capping insulating layer (74, 86, 62, 56) comprises a first portion and a second portion,
the first portion of the capping insulating layer (74, 86, 62, 56) is in contact with the top surface of the buffer insulating layer (58),
the second portion of the capping insulating layer (56) is in contact with a side surface of the buffer insulating layer (58),
a level of a top surface of the first portion of the capping insulating layer (74, 86, 62, 56) is higher than a level of a top surface of the top electrode (54), and
a level of the top surface of the buffer insulating layer (58, see annotation) is lower than the level of the top surface of the top electrode (54)”.
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Regarding claim 19, Wang'281 further teaches, “The semiconductor device of claim 11, wherein
the filling insulating layer (76, silicon oxide) comprises silicon oxide,
the buffer insulating layer (58, “an ultra low-k (ULK) dielectric layer such as porous dielectric materials including but not limited to for example silicon oxycarbide (SiOC)”, ¶ [0021]) comprises a low-k dielectric material, and
the capping insulating layer (74, 86, 62, 56) comprises silicon nitride”.
Regarding independent claim 20, Wang'281 teaches, “A semiconductor device (fig. 1-12; ¶ [0010] - ¶ [0032]), comprising:
a substrate (12, fig. 12) including a cell region (14) and a peripheral region (16);
a cell conductive structure (28) overlapping the cell region (14);
a first peripheral conductive structure (part of element 28 surrounded by element 24 in region 16) overlapping the peripheral region (16);
a bottom electrode contact (34) on the cell conductive structure (28);
a bottom electrode (52) on the bottom electrode contact (34);
a magnetic tunnel junction pattern (36) on the bottom electrode (52);
a top electrode (54) on the magnetic tunnel junction pattern (36);
a second peripheral conductive structure (part of element 28 surrounded by element 26 in region 16) on the first peripheral conductive structure;
a molding insulating layer (24) overlapping the peripheral region (16);
an intervening insulating layer (26) on the molding insulating layer (24);
a buffer insulating layer (58) on the intervening insulating layer (26);
a capping insulating layer (74, 86, 62, 56) in contact with a side surface of the top electrode (54) and a top surface of the buffer insulating layer (58);
a filling insulating layer (76) on the capping insulating layer (74, 86, 62, 56);
a protection insulating layer (78) in contact with the capping insulating layer (74, 86, 62, 56) and the filling insulating layer (76);
a third peripheral conductive structure (60, 82) penetrating the protection insulating layer (78), the capping insulating layer (74, 86, 62, 56), and the buffer insulating layer (58), and
the third peripheral conductive structure (60, 82) being connected to the second peripheral conductive structure; and
a cell conductive line (80) on the top electrode (54),
wherein a dielectric constant of the buffer insulating layer (58, “an ultra low-k (ULK) dielectric layer such as porous dielectric materials including but not limited to for example silicon oxycarbide (SiOC)”, ¶ [0021]) and a dielectric constant of the molding insulating layer (24, SiCN) are smaller than a dielectric constant of the filling insulating layer (76, silicon oxide).
Claims 1, 4, 6 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE; Kevin J. et al. (US 20190013354 A1, hereinafter Lee'354).
Regarding independent claim 1, Lee'354 teaches, “A semiconductor device (fig. 1-9; ¶ [0005] - ¶ [0138]), comprising:
a substrate (fig. 5) including a cell region (504) and a peripheral region (502);
a bottom electrode (590) overlapping the cell region (504);
a magnetic tunnel junction pattern (595, 596) on the bottom electrode (590);
a top electrode (597) on the magnetic tunnel junction pattern;
a buffer insulating layer (532) overlapping the peripheral region (502);
a capping insulating layer (534) in contact with a side surface of the top electrode (597) and a top surface of the buffer insulating layer (532); and
a first peripheral conductive structure (528, 536) penetrating the capping insulating layer (534) and the buffer insulating layer (532), wherein
a level difference between the top surface of the buffer insulating layer (532) and a top surface of the top electrode (597) is smaller than a thickness of the capping insulating layer (534)”.
Regarding claim 4, Lee'354 further teaches, “The semiconductor device of claim 1, further comprising:
a bottom electrode contact (572) connected to the bottom electrode (590);
a lower insulating layer (524) enclosing the bottom electrode contact; and
a molding insulating layer (531) between the lower insulating layer (524) and the buffer insulating layer (532)”.
Regarding claim 6, Lee'354 further teaches, “The semiconductor device of claim 4, further comprising: an intervening insulating layer (534) between the molding insulating layer (531) and the buffer insulating layer (532), wherein a dielectric constant of the intervening insulating layer (534) is higher than a dielectric constant of the buffer insulating layer (532) and a dielectric constant of the molding insulating layer (531) (see ¶ [0075], ¶ [0073], choice of materials)”.
Regarding claim 9, Lee'354 further teaches, “The semiconductor device of claim 1, further comprising: a protection insulating layer (sub layer of 534) on the capping insulating layer (another sub layer of 534), wherein a dielectric constant of the capping insulating layer is smaller than a dielectric constant of the protection insulating layer (referring to ¶ [0075], referring to ¶ [0075], etch stop layer 534 includes multiple sublayers made of silicon nitride, silicon oxide, silicon carbide etc.)”.
Regarding claim 10, Lee'354 further teaches, “The semiconductor device of claim 9, wherein the first peripheral conductive structure (528, 536) penetrates the protection insulating layer (534)”.
Claims 1-2, and 4-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by PENG; Tai-Yen et al. (US 20240206344 A1, hereinafter Peng'344).
Regarding independent claim 1, Peng'344 teaches, “A semiconductor device (fig. 1-19; ¶ [0004] - ¶ [0050]), comprising:
a substrate (fig. 18) including a cell region (CR) and a peripheral region (LR);
a bottom electrode (160) overlapping the cell region;
a magnetic tunnel junction pattern (180) on the bottom electrode;
a top electrode (210) on the magnetic tunnel junction pattern;
a buffer insulating layer (250) overlapping the peripheral region;
a capping insulating layer (280) in (indirect or mechanical) contact with a side surface of the top electrode and a top surface of the buffer insulating layer; and
a first peripheral conductive structure (300, 270) penetrating the capping insulating layer and the buffer insulating layer, wherein
a level difference between the top surface of the buffer insulating layer (250) and a top surface of the top electrode (210) is smaller than a thickness of the capping insulating layer (280).
Regarding claim 2, Peng'344 further teaches, “The semiconductor device of claim 1, further comprising:
a filling insulating layer (240) on the capping insulating layer (280), wherein
the filling insulating layer (240) comprises a filling insulating portion between the top electrode (210) and the buffer insulating layer (250), and
a dielectric constant of the buffer insulating layer (250) is smaller than a dielectric constant of the filling insulating layer (240, ¶ [0038], ¶ [0042])”.
Regarding claim 4, Peng'344 further teaches, “The semiconductor device of claim 1, further comprising:
a bottom electrode contact (150) connected to the bottom electrode;
a lower insulating layer (120) enclosing the bottom electrode contact; and
a molding insulating layer (140) between the lower insulating layer (120) and the buffer insulating layer (240)”.
Regarding claim 5, Peng'344 further teaches, “The semiconductor device of claim 4, wherein
the capping insulating layer (280) comprises a first portion and a second portion,
the first portion of the capping insulating layer (280) is in contact with the top surface of the buffer insulating layer (250), and
the second portion of the capping insulating layer (280) is in (indirect or mechanical) contact with a side surface of the buffer insulating layer (250) and a side surface of the molding insulating layer (120)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Peng'344 as applied to claim 2 above, and further in view of Wang; Hui-Lin et al. (US 20210390993 A1, hereinafter Wang’993).
Regarding claim 3, Peng'344 teaches all the limitations described in claim 2.
But Peng'344 is silent upon the provision of wherein
a top surface of the filling insulating portion comprises a first portion and a second portion,
the first portion of the filling insulating portion is disposed at a level higher than the top surface of the top electrode, and
the second portion of the filling insulating portion is disposed at a level lower than the top surface of the top electrode.
However, Wang’993 teaches all the limitations of claims 1-2. Wang’993 further teaches,
a top surface of the filling insulating portion (402) comprises a first portion and a second portion,
the first portion of the filling insulating portion (402) is disposed at a level higher than the top surface of the top electrode (316), and
the second portion of the filling insulating portion is disposed at a level lower than the top surface of the top electrode (316).
Peng'344 and Wang’993 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Peng'344 with the features of Wang’993 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Peng'344 and Wang’993 to form the MTJ and the spacer according to the teachings of Wang’993 to protect the top electrode from damage during manufacturing process. See Wang’993, ¶ [0003] - [ ¶ [0006].
Conclusion
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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