DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sung Ki Jun et al. (KR 20200102883 A) hereinafter referred to as “Jun” further in view of Yung-Shun Chang et al. (US 11887928 B2) hereinafter referred to as “Chang”.
Regarding Claim 1 Jun teaches
A semiconductor device (Fig 1 element 10) , comprising:
a first die (SP1) including a first physical layer region (the region 617 and 317 are attached to see diagram below) and a second physical layer region (the region the connecting pad and the conductive bump directly to the right of 617 is connected to see diagram below) adjacent to each other;
connecting pads (317 and the connecting pad directly to the right of 317 see diagram below) on a lower surface of the first die (lower surface of SP1);
a connecting wire (170) on the lower surface of the first die;
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through silicon vias (525, 520) configured to penetrate the first die (they penetrate SP1), the through silicon vias including a first through silicon via (527) and a second through silicon via (Fig 1 and 5 element 528 of 525 on the right most side of SP1), the connecting pads having a first connecting pad (317) electrically connected with the first physical layer region, a second connecting pad (the pad to the right of 317 see diagram below) electrically connected with the second physical layer region, a first pad (547) electrically connected with the first through silicon via (527), a second pad (the pad under the second TSV see diagram below) electrically connected with the second through silicon via (528), the connecting wire (170) being electrically connected with the first connecting pad and the first pad. (see diagram to the right)
Although Jun mentions that SP2 can be an internal wiring structure (see Jun attached translation page 9) Jun does not explicitly teach
a rear wiring layer on the first die, the rear wiring layer including a first rear wire; and the first rear wire being electrically connected with the first through silicon via and the second through silicon via
Chang does teach a package structure where
a rear wiring layer (Fig 1 element 273) on the first die (220), the rear wiring layer including a first rear wire(271); and the first rear wire being electrically connected with the first through silicon via and the second through silicon via (230, see diagram below)
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Jun such that the a rear wiring layer on the first die, the rear wiring layer including a first rear wire; and the first rear wire being electrically connected with the first through silicon via and the second through silicon via, as described in Chang because the modified Through silicon vias improve power delivery efficiency by reducing the power supply path (Chang Col. 1 lines 13-15)
Regarding Claim 2 Jun in view of Chang Teaches
The semiconductor device as claimed in claim 1,
Jun further teaches
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wherein the first die (SP1) includes a first side surface and a second side surface configured to face away from the first side surface, the first pad being adjacent to the first side surface, and the second pad being adjacent to the second side surface.(see diagram below)
Regarding Claim 3 Jun in view of Chang Teaches
The semiconductor device as claimed in claim 1,
Jun further teaches
wherein the first connecting pad and the first pad are adjacent to each other. (Fig 1 or see previous diagrams)
Regarding Claim 5 Jun in view of Chang Teaches
The semiconductor device as claimed in claim 3,
Jun further teaches
wherein the connecting wire (170) includes a redistribution layer. (Jun calls 170 a redistribution layer pattern, see Jun)
Regarding Claim 8 Jun in view of Chang Teaches
The semiconductor device as claimed in claim 1,
Jun further teaches
wherein the first die is a processor chip. (at least a portion of SP1(300) can be a processor see Jun Page 6 )
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jun in view of Chang as applied to claim 1 above, and further in view of Szu Wei Lu et al. (US 20120199974 A1) hereinafter referred to as “Lu”.
Regarding Claim 4 Jun in view of Chang Teaches
The semiconductor device as claimed in claim 1,
Jun teaches that the connecting wire is a redistribution layer pattern 170 but Jun does not mention it including under bump metal.
Lu teaches a package structure
wherein the connecting wire (Fig 3 element 50) includes an under bump metal (45).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Jun in view of Chang such that the connecting wire includes an under bump metal, as described in Lu because the modification allows for less concern around cracking. (Lu Para [0011])
Claim(s) 6, 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jun in view of Chang as applied to claim 1 above, and further in view of Seung Hyun Lee et al. (US 20070222050 A1) hereinafter referred to as “Lee”.
Regarding Claim 6 Jun in view of Chang teaches
The semiconductor device as claimed in claim 1,
Jun does not teach
further comprising: a second die on the rear wiring layer, a first region and a second region defined on an upper surface of the first die, the first region being a region on which the second die is positioned, the second region being a region on which the second die is not positioned, the first rear wire being provided on the second region.
Lee does teach a stacked package structure that
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further comprising: a second die (420) on the rear wiring layer (418 because it contains wiring line 417), a first region (see diagram below) and a second region (see diagram below) defined on an upper surface of the first die, the first region being a region on which the second die is positioned, the second region being a region on which the second die is not positioned, the first rear wire being provided on the second region.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Jun in view of Chang such that the second die is positioned on the first region, as described in Lee because the modification allows for the options in the placement of the connection points as well as the smaller size allows stress to be dispersed thus improving reliability. (Lee Para [0038])
Regarding Claim 7 Jun in view of Chang further in view of Lee teaches
The semiconductor device as claimed in claim 6,
Jun does not explicitly teach
wherein the first region is on a central portion of the upper surface of the first die.
Lee further teaches
wherein the first region is on a central portion of the upper surface of the first die. (see previous diagram)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Jun in view of Chang further in view of Lee such that the first region is on a central portion of the upper surface of the first die, as described in Lee because the modification allows for the options in the placement of the connection points as well as the smaller size allows stress to be dispersed thus improving reliability. (Lee Para [0038])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hsu; Shih Ping (US 20100032827 A1), Hyung; Sujung (US 20250062183 A1), KIM; SUNJAE (US 20230035032 A1), Oh; Seungyeol (US 20220208649 A1), Kim; Sun Chul (US 20200135683 A1)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Thursday, 7:30a.m. - 5:00p.m. ET..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAIME LYNN SPRENGER/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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