DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 28, 2026 has been entered.
Response to Amendment
The amendment filed May 8, 2026 has been entered. Claims 1, 3-8, 10-14, and 16-20 remain pending in this application. Claims 2, 9, and 15 have been cancelled at applicant’s request. Claims 1, 4, 7-8, 11-12, 14, and 16 have been amended (Note: Independent Claim 14 is improperly marked as ‘Previously Presented’ despite amendments). No claims have been added. No new matter has been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-5, 8, 10, 14, and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 11,798,638 B2 to Xiang Yang, et al. (hereafter Yang) in view of US 6,327,202 B1 to Frankie F. Roohparvar (hereafter Roohparvar) and further in view of US 6,480,419 B2 to Yeong-Tack Lee (hereafter Lee 419).
Regarding Amended Independent Claim 1, Yang discloses a storage system, comprising:
a set of storage elements (Disclosing a set of storage elements: Yang, Figure 4J);
a plurality of bitlines,
each bitline of the plurality of bitlines being associated with a respective storage element of the set of storage elements (A set of bitlines 411-414 associated with a set of respective storage elements: Yang, Figure 4A); and
one or more control circuits (Control circuits 260, 220, and 230: Yang, Figure 2B), the one or more control circuits configured to
during a memory operation performed on the set of storage elements (Disclosing charging bitlines during a programming operation: Yang, col.3:5-6):
charge the plurality of bitlines to a first voltage level (Teaching charging a first set of bitlines to a high voltage, charging a second set of bitlines to a higher voltage, and then further charging the first set of bitlines to match the charge in the second set: Yang, col.3:7-18; Broadest reasonable interpretation does not require the selected and unselected bitlines be charged simultaneously. The limitation is the ‘set of bitlines’, set implying more than one but not necessarily all bitlines, at some point be charged to ‘a high voltage,’ implying a single high voltage. Yang discloses both.).
Yang does not disclose, subsequent to charging the set of bitlines to a high voltage level, discharging select lines associated with the selected storage elements from the first voltage level to a second voltage level that is between a ground voltage and the first voltage. Roohparvar, however, teaches a storage system with a control circuit configured to:
charge the plurality of bitlines to a first voltage level (Charging the plurality of bitlines to a first voltage level Vcc: Roohparvar, col.6:23-24; Note, this is analogous to the same operation in Yang, repeated here to establish Vcc as a ‘first voltage level.’)
discharge a set of bitlines of the plurality of bitlines (Discharging some of the bitlines: Roohparvar, col.6:25-27)
that are associated with selected storage elements of the set of storage elements (Teaching the reduced voltage lines being used to read the selected storage elements: Roohparvar, col.9:29-34)
from the first voltage level to a second voltage level that is between a ground voltage and the first voltage (The discharged bitlines going from first voltage Vcc to second voltage Vcc/2, which is less than Vcc but greater than ground: Roohparvar, col.6:30-32) and
while bitlines of the set are discharged to the second level (The discharged bitlines going from first voltage Vcc to second voltage Vcc/2, which is less than Vcc but greater than ground: Roohparvar, col.6:30-32).
Roohparvar teaches this approach improves read operations of non-volatile memory by leveraging the capacitive features of the bitlines (Roohparvar, col.6:3-5). Further, it allows for pre-charge voltage levels to be adjusted after manufacture without costly mask changes and still accounting for manufacturing variations (Roohparvar, col.6:62-67). Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the capacitive charging technique of Roohparvar with the bitline management system of Yang, with a reasonable expectation of success. Both inventions are well known in the field of bitline charge management in non-volatile memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Neither Yang nor Roohparvar teaches charging the plurality of bitlines to the first voltage level, floating the plurality of bitlines, and then, based on output from one or more data latches, a discharge path is formed for the set of bitlines only and there is no discharge path in bitlines of the plurality of bitlines that are not in the set such that the bitlines that are not in the set stay at the first voltage level while bitlines of the set are discharged to the second level. Lee 419, however, discloses a storage system wherein:
in response to the plurality of bitlines reaching the first voltage level, float the plurality of bitlines (Disclosing charging all bitlines to a first high voltage and then, separately, choosing to discharge certain lines and leaving the other charged: Lee 419, col.5:4-8); and
wherein,
based on output from one or more data latches (Retaining or discharging voltage based on respective data bits stored: Lee 419, col.5:4-8),
a discharge path is formed for the set of bitlines only (Discharging only select bitlines: Lee 419, col.12:19-21) and
there is no discharge path in bitlines of the plurality of bitlines that are not in the set such that the bitlines that are not in the set stay at the first voltage level (Non-discharged lines remain at the first charged voltage: Lee 419, col.12:17-22).
Lee 419 teaches managing the charging/discharging of bitlines in this manner limits discharging or charging currents and avoid the peak currents that cause noise (Lee 419, col.10:20-24). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of this application to apply the noise minimizing charging/discharging method of Lee 419 to the bitline management system of Yang, with a reasonable expectation of success. Both inventions are well known in the realm of bitline charge management systems in non-volatile memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 3 and the substantially similar limitations of Claim 10 and Amended Claim 16, Yang discloses the storage system of claim 1, wherein the one or more control circuits is further configured to:
select a voltage source associated with the first voltage level (Disclosing a first high voltage source: Yang, col.12:12-13).
Regarding Amended Claim 4 and the substantially similar limitations of Claim 17, Yang and Roohparvar disclose the storage system of claim 1, further comprising:
a set of sense circuits,
each sense circuit of the set of sense circuits being connected to a respective bitline of the plurality of bitlines (Disclosing bitline BL connected to a sense node through transistor 1204: Yang, Figure 12A with col.31:1-3) and including:
a first transistor configured to isolate a sense circuit from the first voltage level (First transistor 1206 capable of isolating the sense circuit through transistor 1204 from first high voltage VDD_SA: Yang, Figure 12A with col.31:1-3); and
a second transistor configured to discharge one of the bitlines of the set of bitlines (Second transistor 1202 capable of discharging the bitline to VSS: Yang, Figure 12A with col.31:1-3)
from the first voltage level to the second voltage level (Discharging the bitline from the first voltage Vcc to the second voltage Vcc/2: Roohparvar, col.6:30-32).
Regarding Claim 5 and the substantially similar limitations of Claim 18, Yang discloses the storage system of claim 3, wherein the one or more control circuits is further configured to:
apply different voltages to gates of second transistors of sense circuits associated with the selected storage elements (Disclosing programming cells via a series of increasing pulse voltages: Yang, col.14:4-6).
Regarding Amended Independent Claim 8, Yang discloses a method of operating a non-volatile semiconductor memory device, the method comprising:
charging a plurality of bitlines to a first voltage level (Disclosing charging bitlines during a programming operation: Yang, col.3:5-6),
each bitline of the plurality of bitlines being associated with a respective storage element of a set of storage elements (A set of bitlines 411-414 associated with a set of respective storage elements: Yang, Figure 4A).
Yang does not disclose, subsequent to charging the set of bitlines to a high voltage level, discharging select lines associated with the selected storage elements from the first voltage level to a second voltage level that is between a ground voltage and the first voltage. Roohparvar, however, teaches a storage system with a control circuit configured to:
charge the plurality of bitlines to a first voltage level (Charging the plurality of bitlines to a first voltage level Vcc: Roohparvar, col.6:23-24; Note, this is analogous to the same operation in Yang, repeated here to establish Vcc as a ‘first voltage level.’)
discharge a set of bitlines of the plurality of bitlines (Discharging some of the bitlines: Roohparvar, col.6:25-27)
that are associated with selected storage elements of the set of storage elements (Teaching the reduced voltage lines being used to read the selected storage elements: Roohparvar, col.9:29-34)
from the first voltage level to a second voltage level that is between a ground voltage and the first voltage (The discharged bitlines going from first voltage Vcc to second voltage Vcc/2, which is less than Vcc but greater than ground: Roohparvar, col.6:30-32) and
while bitlines of the set are discharged to the second level (The discharged bitlines going from first voltage Vcc to second voltage Vcc/2, which is less than Vcc but greater than ground: Roohparvar, col.6:30-32).
Roohparvar teaches this approach improves read operations of non-volatile memory by leveraging the capacitive features of the bitlines (Roohparvar, col.6:3-5). Further, it allows for pre-charge voltage levels to be adjusted after manufacture without costly mask changes and still accounting for manufacturing variations (Roohparvar, col.6:62-67). Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the capacitive charging technique of Roohparvar with the bitline management system of Yang, with a reasonable expectation of success. Both inventions are well known in the field of bitline charge management in non-volatile memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Neither Yang nor Roohparvar teaches charging the plurality of bitlines to the first voltage level, floating the plurality of bitlines, and then, based on output from one or more data latches, a discharge path is formed for the set of bitlines only and there is no discharge path in bitlines of the plurality of bitlines that are not in the set such that the bitlines that are not in the set stay at the first voltage level while bitlines of the set are discharged to the second level. Lee 419, however, discloses a storage system wherein:
in response to the plurality of bitlines reaching the first voltage level, float the plurality of bitlines (Disclosing charging all bitlines to a first high voltage and then, separately, choosing to discharge certain lines and leaving the other charged: Lee 419, col.5:4-8); and
wherein,
based on output from one or more data latches (Retaining or discharging voltage based on respective data bits stored: Lee 419, col.5:4-8),
a discharge path is formed for the set of bitlines only (Discharging only select bitlines: Lee 419, col.12:19-21) and
there is no discharge path in bitlines of the plurality of bitlines that are not in the set such that the bitlines that are not in the set stay at the first voltage level (Non-discharged lines remain at the first charged voltage: Lee 419, col.12:17-22).
Lee 419 teaches managing the charging/discharging of bitlines in this manner limits discharging or charging currents and avoid the peak currents that cause noise (Lee 419, col.10:20-24). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of this application to apply the noise minimizing charging/discharging method of Lee 419 to the bitline management system of Yang, with a reasonable expectation of success. Both inventions are well known in the realm of bitline charge management systems in non-volatile memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Independent Claim 14, Yang discloses an apparatus, comprising:
a set of storage elements (Disclosing a set of storage elements: Yang, Figure 4J);
a plurality of bitlines,
each bitline of the plurality of bitlines being associated with a respective storage element of the set of storage elements (A set of bitlines 411-414 associated with a set of respective storage elements: Yang, Figure 4A); and
a means for performing a memory operation on the set of storage elements, the means for performing the memory operation on the set of storage elements being configured to:
charge the plurality of bitlines to a first voltage level (Teaching charging a first set of bitlines to a high voltage, charging a second set of bitlines to a higher voltage, and then further charging the first set of bitlines to match the charge in the second set: Yang, col.3:7-18).
Yang does not disclose, subsequent to charging the set of bitlines to a high voltage level, discharging select lines associated with the selected storage elements from the first voltage level to a second voltage level that is between a ground voltage and the first voltage. Roohparvar, however, teaches a storage system with a control circuit configured to:
charge the plurality of bitlines to a first voltage level (Charging the plurality of bitlines to a first voltage level Vcc: Roohparvar, col.6:23-24; Note, this is analogous to the same operation in Yang, repeated here to establish Vcc as a ‘first voltage level.’)
discharge a set of bitlines of the plurality of bitlines (Discharging some of the bitlines: Roohparvar, col.6:25-27)
that are associated with selected storage elements of the set of storage elements (Teaching the reduced voltage lines being used to read the selected storage elements: Roohparvar, col.9:29-34)
from the first voltage level to a second voltage level that is between a ground voltage and the first voltage (The discharged bitlines going from first voltage Vcc to second voltage Vcc/2, which is less than Vcc but greater than ground: Roohparvar, col.6:30-32) and
while bitlines of the set are discharged to the second level (The discharged bitlines going from first voltage Vcc to second voltage Vcc/2, which is less than Vcc but greater than ground: Roohparvar, col.6:30-32).
Roohparvar teaches this approach improves read operations of non-volatile memory by leveraging the capacitive features of the bitlines (Roohparvar, col.6:3-5). Further, it allows for pre-charge voltage levels to be adjusted after manufacture without costly mask changes and still accounting for manufacturing variations (Roohparvar, col.6:62-67). Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the capacitive charging technique of Roohparvar with the bitline management system of Yang, with a reasonable expectation of success. Both inventions are well known in the field of bitline charge management in non-volatile memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Neither Yang nor Roohparvar teaches charging the plurality of bitlines to the first voltage level, floating the plurality of bitlines, and then, based on output from one or more data latches, a discharge path is formed for the set of bitlines only and there is no discharge path in bitlines of the plurality of bitlines that are not in the set such that the bitlines that are not in the set stay at the first voltage level while bitlines of the set are discharged to the second level. Lee 419, however, discloses a storage system wherein:
in response to the plurality of bitlines reaching the first voltage level, float the plurality of bitlines (Disclosing charging all bitlines to a first high voltage and then, separately, choosing to discharge certain lines and leaving the other charged: Lee 419, col.5:4-8); and
wherein,
based on output from one or more data latches (Retaining or discharging voltage based on respective data bits stored: Lee 419, col.5:4-8),
a discharge path is formed for the set of bitlines only (Discharging only select bitlines: Lee 419, col.12:19-21) and
there is no discharge path in bitlines of the plurality of bitlines that are not in the set such that the bitlines that are not in the set stay at the first voltage level (Non-discharged lines remain at the first charged voltage: Lee 419, col.12:17-22).
Lee 419 teaches managing the charging/discharging of bitlines in this manner limits discharging or charging currents and avoid the peak currents that cause noise (Lee 419, col.10:20-24). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of this application to apply the noise minimizing charging/discharging method of Lee 419 to the bitline management system of Yang, with a reasonable expectation of success. Both inventions are well known in the realm of bitline charge management systems in non-volatile memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 6 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 11,798,638 B2 to Xiang Yang, et al. (hereafter Yang), US 6,327,202 B1 to Frankie F. Roohparvar (hereafter Roohparvar), and US 6,480,419 B2 to Yeong-Tack Lee (hereafter Lee 419) in view of US 2010/0195387 A1 to Ki Tae Park (hereafter Park).
Regarding Claim 6 and the substantially similar limitations of Claim 19, Yang discloses the storage system of Claim 3, but fails to disclose the further limitations of Claim 6. Park, however, discloses a memory array as in Claim 3, wherein the one or more control circuits is further configured to:
apply different pulse widths to gates of second transistors of sense circuits associated with the selected storage elements (Disclosing different pulses widths during a programming operation: Park, Figure 5).
Lee discloses adjusting the width of a program pulse, rather than the magnitude, minimizes the effects of program disturbance in neighboring cells (Park, ¶[0061]).
Therefore, it would have been obvious to one have ordinary skill in the art, before the effective filing date of this application, to combine the ISPP pulse width scheme of Park with the bitline voltage control system of Yang, with a reasonable expectation of success. Both inventions are well known in the field of memory programming operations and both are intended to minimize the effects of program disturb on neighboring cells, and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 7, 11-13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 11,798,638 B2 to Xiang Yang, et al. (hereafter Yang), US 6,327,202 B1 to Frankie F. Roohparvar (hereafter Roohparvar), and US 6,480,419 B2 to Yeong-Tack Lee (hereafter Lee 419) in view of US 8,824,229 B2 to Hyun Joo Lee, et al. (hereafter Lee).
Regarding Amended Claim 7 and the substantially similar limitations of Claims 13 and 20, Yang discloses the storage system of Claim 1 but fails to disclose the remaining limitations of Claim 7. Lee, however, discloses a memory storage system as in Claim 1, wherein the one or more control circuits is further configured to:
discharge the bitlines of the set of bitlines for a predetermined discharge period (Disclosing a set time duration D1 and D2 during which time bitline BL is selectively discharged: Lee, Figure 3).
Lee teaches this bitline pre-discharging operation improves efficiency by reducing the time required to fully discharge the bitline (Lee, col.4:22-25). Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the efficient pre-discharge operation of Lee with the bitline control system of Yang, with a reasonable expectation of success. Both inventions are well known in the field of bitline voltage management and the combination of known inventions with predictable outcomes is obvious and not patentable.
Regarding Amended Claim 11, Yang discloses the method of claim 8 but fails to disclose the further limitations of Claim 11. Roohparvar discloses discharging the bitline from the first voltage to the second voltage (Discharging the bitline from the first voltage Vcc to the second voltage Vcc/2: Roohparvar, col.6:30-32). Further, Lee discloses a method as in Claim 8, further comprising:
applying different voltages to gates of transistors of sense circuits associated with the selected storage elements, wherein the transistors are configured to discharge the first voltage level from a bitline (Disclosing bitline BL discharge is reliant on separate signals ACT, SIGNAL_A, and BLDIS_E: Lee, col.4:26-33) to the second voltage.
Lee teaches this bitline pre-discharging operation improves efficiency by reducing the time required to fully discharge the bitline (Lee, col.4:22-25). Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the efficient pre-discharge operation of Lee with the bitline control system of Yang, with a reasonable expectation of success. Both inventions are well known in the field of bitline voltage management and the combination of known inventions with predictable outcomes is obvious and not patentable.
Regarding Amended Claim 12, Yang discloses the method of claim 8, but fails to disclose the further limitations of Claim 12. Roohparvar discloses discharging the bitline from the first voltage to the second voltage (Discharging the bitline from the first voltage Vcc to the second voltage Vcc/2: Roohparvar, col.6:30-32). Further, Lee discloses a method as in Claim 8, further comprising:
applying different pulse widths to gates of transistors of sense circuits associated with the selected storage elements, wherein the transistors are configured to discharge bitlines of the set of bitlines from the first voltage level to the second voltage level (Disclosing applying a signal to discharge the bitlines during the period before the active ACT signal is enabled: Lee, col.4:15-17).
Lee teaches this bitline pre-discharging operation improves efficiency by reducing the time required to fully discharge the bitline (Lee, col.4:22-25). Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the efficient pre-discharge operation of Lee with the bitline control system of Yang, with a reasonable expectation of success. Both inventions are well known in the field of bitline voltage management and the combination of known inventions with predictable outcomes is obvious and not patentable.
Response to Arguments
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
KR 20180085419 A to Kim Wan Dong, et al.: Teaching a page buffer that applies positive voltages to all wordlines, floats the wordlines upon reaching the high voltage, and discharges select lines.
US 6,781,904 B2 to Seung-Keun Lee, et al.: Disclosing a low voltage memory device including high and low voltage transistors in the discharge circuit.
US 8,130,551 B2 to Ken Oowada, et al.: Disclosing precharging all bitlines and then leaving them to float being common during memory array operations.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/UYEN SMET/Primary Examiner, Art Unit 2824
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