DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species I, sub-species B (Figs. 9A-14), which applicant identified claims 1-23 as encompassing, in the reply filed on 6/1/2026 is acknowledged. The traversal is on the ground(s) that the search and examination of the entire application can be made without serious burden and that independent claim 24 shares many of the same structural elements as independent claims 1 and 12. This is not found persuasive because while the method independent claim 24 and device independent claims 1 and 12 may share some structural similarities, they are distinct as the device claims 1 and 12 can be made by another and materially different process from that claim 24 as detailed in paragraph 3 of the Office action mailed 4/8/2026. Examiner further indicated that there is a serious search and/or examination burden as the inventions require different fields of search as detailed in paragraphs 2 and 4 of the aforementioned Office action.
The requirement is still deemed proper and is therefore made FINAL.
Claims 24-30 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention and/or species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 6/1/2026.
Examiner notes that claims 5-7 and 13-15 are drawn to non-elected Species II and not elected Species I. Therefore, claims 5-7 and 13-15 will not be examined as they are withdrawn as not being directed to the elected species.
Claim Objections
Claim 12 is objected to because of the following informalities: in line 3, “first horizontal” should be amended to read –a first horizontal –. Appropriate correction is required.
Claim 12 is objected to because of the following informalities: in line 4, “first horizontal” should be amended to read –a first horizontal –. Appropriate correction is required.
Claim 12 is objected to because of the following informalities: in line 13, “dielectric” should be amended to read – dielectric material–. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9, 11, 12, 16-19, 21, and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2022/0077151 and Lee hereinafter).
As to claims 1-4, 9, and 11: Lee discloses [claim 1] a memory device (Figs. 9A-9B; 400; [0078]), comprising: a twin channel, horizontally oriented access device (TR has two channels, CH1 and CH2, and is oriented horizontally along D2; [0079]-[0080]) having; a first source/drain region (top SR; [0080]) and a second source/drain region (top DR’; [0080]) separated by a first channel region (CH2; [0080]), being operatively controlled by a first gate (WL surrounding CH2; [0079]-[0080]) separated from the first channel region (CH2) by a first gate dielectric (GD; [0074]); and a third source/drain region (bottom SR; [0080]) and a fourth source/drain region (bottom DR’; [0080]) separated by a second channel region (CH1; [0080]), being operatively controlled by a second gate (WL surrounding CH1) separated from the second channel region (CH1) by a second gate dielectric (GD); a first horizontally oriented storage node (top half of CAP; [0079]) coupled to the second source/drain region (top DR’) of the twin channel access device; and a second horizontally oriented storage node (bottom half of CAP, claim doesn’t state that the storage nodes need to be spatially separated from one another, each “fin” of CAP shown is interpreted to be a storage node; [0079]) coupled to the fourth source/drain region (bottom DR’) of the twin channel access device (TR); [claim 2] wherein the first (WL surrounding CH2) and the second (WL surrounding CH1) gates are electrically connected (as WL); [claim 3] wherein the first (WL surrounding CH2) and the second (WL surrounding CH1) gates are horizontally oriented gates (along D3; [0079]); [claim 4] wherein the first source/drain region (top SR) of the twin channel access device (TR) and the third source/drain region (bottom SR) of the twin channel access (TR) device are coupled (through BLC; [0081]) to a vertically oriented (along D1; [0079]) digit line (BL; [0079]); [claim 9] wherein: the first (CH2) and the second channel (CH1) regions having a cumulative channel width doubling a current on ("Ion") value relative to a same horizontal memory device layout architecture having only a single channel horizontal access device, using a same set of operating parameters (as the structure of the channels is the same as the claimed and disclosed device, the cumulative channel width of CH1 and CH2 of Lee will behave in the same way as claimed (have the same properties as that claimed and disclosed), i.e. double a current on value relative to a single channel horizontal access device); [claim 11] wherein the memory device (400) comprises a vertically oriented three-dimensional (3D), multi-tiered memory array (Lee discloses that 400 can be a memory array as shown in Fig. 7, which is a 3D multi-tiered array that is vertically oriented along D1 with each tier comprising one 400; [0085]) with each tier having twin channel, horizontally oriented access devices (TR) and first and second horizontally oriented storage nodes (top and bottom half of a respective CAP).
As to claims 12, 16-19, 21, and 22: Lee discloses [claim 12] a memory device (Figs. 7 and 9A-9B; 400; [0078]), comprising: a horizontally oriented access device (Fig. 9B; TR is oriented horizontally along D2; [0079]-[0080]) having a vertically stacked structure (Lee discloses that 400 can be a memory array as shown in Fig. 7, which is a 3D multi-tiered array that is vertically oriented along D1 with each tier comprising one 400; [0085]), comprising: first horizontal gate portion (Fig. 9B; top SG; [0041]); first horizontal channel (CH2; [0080]) horizontally separating a first source/drain region (top SR; [0080]) and a second source/drain region (top DR’; [0080]), and separated from the first horizontal gate (top SG) by a dielectric material (GD; [0074]); a second horizontal gate portion (middle SG; [0041]) separated from the first horizontal channel (CH2) by the dielectric material (GD); a second horizontal channel (CH1; [0080]) horizontally separating a third source/drain region (bottom SR; [0080]) and a fourth source/drain region (bottom DR’; [0080]), and separated from the second horizontal gate (middle SG) by the dielectric material (GD); and a third horizontal gate portion (bottom SG; [0041]) separated from the second horizontal channel (CH1) by the dielectric (GD); a first horizontally oriented storage node (top half of CAP; [0079]) coupled to the second source/drain region (top DR’); and a second horizontally oriented storage node (bottom half of CAP, claim doesn’t state that the storage nodes need to be spatially separated from one another, each “fin” of CAP shown is interpreted to be a storage node; [0079]) coupled to the fourth source/drain region (bottom DR’); [claim 16] wherein the horizontally oriented access device (TR) is a thin film transistor (TFT) (the device as shown is the same as that claimed and disclosed in structure and is thus interpreted to be a TFT; [0079]) and the first and the second horizontally oriented storage nodes (top half of CAP and bottom half of CAP) are horizontally oriented capacitors (CAP; [0079]) located in a same horizontal tier (tier shown in Fig. 9B) to form a twin transistor, twin capacitor (2T2C) memory cell (structure shown is interpreted to be 2T2C as it is the same as claimed and as disclosed in the instant application); [claim 17] wherein the memory device (400) comprises a vertically oriented three-dimensional (3D), multi-tiered memory array (Lee discloses that 400 can be a memory array as shown in Fig. 7, which is a 3D multi-tiered array that is vertically oriented along D1 with each tier comprising one 400; [0085]) with each tier having twin transistor, twin capacitor (2T2C) memory cells (as shown); [claim 18] wherein the first source/drain region (top SR) of the first horizontal channel (CH2) and the third source/drain region (bottom SR) of the second horizontal channel (CH1) are electrically coupled (through BLC; [0081]) to a vertically oriented (along D1; [0079]) digit line (BL; [0079]); [claim 19] wherein: the second source/drain region (top DR’) of the first horizontal channel (CH2) is coupled to a bottom electrode (SN is interpreted to be a bottom electrode as it is surrounded by the dielectric DE and upper electrode PN; [0045]) of the first horizontally oriented storage node (upper half of CAP); and the fourth source/drain region (bottom DR’) of the second horizontal channel (CH1) is coupled to a bottom electrode (SN is interpreted to be a bottom electrode as it is surrounded by the dielectric DE and upper electrode PN; [0045]) of the second horizontally oriented storage node (bottom half of CAP); [claim 21] wherein the first (top SG) and second (middle SG) horizontal gates are electrically coupled together (as WL; [0041]) and form gate all around (GAA) structures (WL) opposing the first (CH2) and the second (CH1) horizontal channels; [claim 22] wherein when actuated the GAA structures invert a conductive path in opposing sides of the first and the second horizontal channels to double a width of the conductive path in the first and the second horizontal channels together with the first and the third horizontal gates (this is an inherent feature of the device as the structure of Lee is the same as that claimed and disclosed and thus will inherently operate the same way).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Pillarisetty et al (US 2019/0348466 and Pillarisetty hereinafter).
Although the structure disclosed by Lee shows substantial features of the claimed invention (discussed in paragraph 11 above), it fails to expressly disclose:
wherein a power supply operating voltage ("Vccp") for the memory device is less than 2.0 volts.
Pillarisetty discloses that memory arrays can incorporate transistors that have operating voltages that are less than 1 volt or less ([0027]).
Given the teachings of Pillarisetty, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lee by employing the well-known or conventional features of DRAM cell fabrication, such as displayed by Pillarisetty, by employing a transistor with an operating voltage less than or equal to 1 volt in order to allow the memory device to become more energy efficient ([0027]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Madan et al (US 2024/0078195 and Madan hereinafter).
Although the structure disclosed by Lee shows substantial features of the claimed invention (discussed in paragraph 12 above), it fails to expressly disclose:
wherein the first and the second horizontally oriented storage nodes are horizontally oriented, ferroelectric storage nodes.
Lee discloses storage nodes with dielectric materials.
Madan discloses that instead of linear dielectrics, ferroelectric dielectrics can be used ([0027]).
Given the teachings of Madan, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lee by employing the well-known or conventional features of Fe-RAM cell fabrication, such as displayed by Madan, by employing a storage node/capacitor using a ferroelectric dielectric in order to provide a storage node with more density and better performance ([0027]).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kang et al (US 2021/0249415 and Kang hereinafter).
Although the structure disclosed by Lee shows substantial features of the claimed invention (discussed in paragraph 12 above), it fails to expressly disclose:
wherein the first and the second horizontally oriented storage nodes each have a horizontal length of less than two hundred (200) nanometers (nm).
Kang discloses in [0105] that a horizontal length of the capacitor can be in a range of 200 nm to 1500 nm.
The size of the capacitor affects the amount of storage available in the capacitor and is thus a result effective variable.
Thus, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose a length of the capacitor such that it is around 200 nm balancing a need for storage capacity with overall footprint in the device of each capacitor in the array. As stated in MPEP 2144.05(I), “a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985) (Court held as proper a rejection of a claim directed to an alloy of "having 0.8% nickel, 0.3% molybdenum, up to 0.1% iron, balance titanium" as obvious over a reference disclosing alloys of 0.75% nickel, 0.25% molybdenum, balance titanium and 0.94% nickel, 0.31% molybdenum, balance titanium. "The proportions are so close that prima facie one skilled in the art would have expected them to have the same properties."). See also Warner-Jenkinson Co., Inc. v. Hilton Davis Chemical Co., 520 U.S. 17, 41 USPQ2d 1865 (1997) (under the doctrine of equivalents, a purification process using a pH of 5.0 could infringe a patented purification process requiring a pH of 6.0-9.0); In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%); In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205-206 (CCPA 1946) (prior art showed an angle in a groove of up to 90° and an applicant claimed an angle of no less than 120°); In re Becket, 88 F.2d 684 (CCPA 1937) ("Where the component elements of alloys are the same, and where they approach so closely the same range of quantities as is here the case, it seems that there ought to be some noticeable difference in the qualities of the respective alloys."); In re Dreyfus, 73 F.2d 931, 934, 24 USPQ 52, 55 (CCPA 1934)(the prior art, which taught about 0.7:1 of alkali to water, renders unpatentable a claim that increased the proportion to at least 1:1 because there was no showing that the claimed proportions were critical); In re Lilienfeld, 67 F.2d 920, 924, 20 USPQ 53, 57 (CCPA 1933)(the prior art teaching an alkali cellulose containing minimal amounts of water, found by the Examiner to be in the 5-8% range, the claims sought to be patented were to an alkali cellulose with varying higher ranges of water (e.g., "not substantially less than 13%," "not substantially below 17%," and "between about 13[%] and 20%"); K-Swiss Inc. v. Glide N Lock GmbH, 567 Fed. App'x 906 (Fed. Cir. 2014)(reversing the Board's decision, in an appeal of an inter partes reexamination proceeding, that certain claims were not prima facie obvious due to non-overlapping ranges); In re Brandt, 886 F.3d 1171, 1177, 126 USPQ2d 1079, 1082 (Fed. Cir. 2018)(the court found a prima facie case of obviousness had been made in a predictable art wherein the claimed range of "less than 6 pounds per cubic feet" and the prior art range of "between 6 lbs./ft3 and 25 lbs./ft3" were so mathematically close that the difference between the claimed ranges was virtually negligible absent any showing of unexpected results or criticality.).” Therefore, as the lower end of the disclosed range (200 nm) is close to the claimed range of less than 200 nm, the properties are expected to be similar due to the closeness of the values and as applicant has not established that the range is critical and/or exhibits unexpected results.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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