DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over in view of KWON et al. (US PG Pub 2022/0122908, hereinafter Kwon1 in view of Lin et al. (US PG Pub 2024/0094104) and KWON et al. (US PG Pub 2023/0099351, hereinafter Kwon2).
Regarding claim 1, figure 6 of Kwon1 discloses a semiconductor package comprising:
an interposer (210);
metal wiring (230) at the interposer;
a first bump disposed (310) at the metal wiring;
a semiconductor chip (100) disposed at the first bump and including a pad (120) electrically coupled to the first bump; and
a second bump (350) disposed at the metal wiring.
Kwon1 does not explicitly disclose a silicon interposer.
In the same field of endeavor, Lin discloses silicon as a suitable material for an interposer (¶ 51).
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to include silicon in the interposer as taught by Lin for the purpose of choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success (KSR International Co. v. Teleflex Inc. 82 USPQ2d 1385 (2007)).
Kwon1 does not explicitly disclose a photosensitive resin disposed at the silicon interposer and including an opening portion; the second bump is at the metal wiring in a region that overlaps the photosensitive resin in a plan view.
In the same field of endeavor, figure 1B of Kwon2 discloses a solder resist layer (114A/114B) including an opening portion; with a metal wiring (112) disposed in the opening portion and a second bump (140) at the metal wiring in a region that overlaps the solder resist in a plan view.
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the solder resist layer on the interposer of Kwon1 as taught by Kwon2 for the purpose of preventing contact defect issues (¶ 83).
Finally, it is well known in the art that photosensitive resin is material for solder resist and it would have been obvious to use it for the solder resist layer of Kwon 2 for the purpose of choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success (KSR International Co. v. Teleflex Inc. 82 USPQ2d 1385 (2007)).
Regarding claim 2, the combined references (particularly figure 1B of Kwon2) discloses an end portion of the photosensitive resin in the opening portion (of 114B) is on an outer side with respect to an outer edge of the semiconductor chip (120) and on an inner side with respect to an edge of the second bump (140).
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Kwon1 in view of Lin and Kwon2, as applied to claim 2, further in view of MYUNG et al. (US PG Pub 2023/0132054, hereinafter Myung).
Regarding claim 3, Kwon1 does not explicitly disclose a dummy pad disposed apart from the pad (120) on a surface of the semiconductor chip (100) where the pad is disposed;
a dummy bump coupled to the dummy pad; and
a dummy metal layer disposed between the dummy bump and the silicon interposer in a region of the opening portion.
In the same field of endeavor, figures 1A and 1B of Myung disclose a dummy pad (252) disposed apart from a pad (251) on a surface of a semiconductor chip (300) where the pad is disposed;
a dummy bump (320) coupled to the dummy pad; and
a dummy metal layer (112) disposed between the dummy bump and the interposer (100).
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the dummy pad, bump, and metal layer (which would be in a region of the opening portion since the entire die of Kwon1 is in the opening portion) as taught by Myung for the purpose of preventing substrate warpage (¶ 114).
Regarding claim 4, Myung discloses he dummy bump (320) is in an electrically floating state (¶ 34).
Regarding claim 5, figure 1A of Myung discloses the dummy bump (320) includes a plurality of dummy bumps, and the plurality of dummy bumps are disposed in a lattice pattern at the dummy metal layer.
Regarding claim 6, figure 1A of Myung discloses the dummy bump (320) includes a plurality of dummy bumps, and the plurality of dummy bumps are disposed at a higher density in a region that overlaps a heat-generating body of the semiconductor chip than in a region that does not overlap the heat-generating body (regions not overlapping the semiconductor chip).
Conclusion
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817