Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in People’s Republic of China on 04/20/2023. It is noted, however, that applicant has not filed a certified copy of the Foreign application as required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Species A (Claims 1-4 and 12-15) in the reply filed on 3/23/2026 is acknowledged.
Claims 1-4 and 12-15 are elected for examination and claims 5-11 and 16-20 are withdrawn from consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US Pub. No. 2023/0044202 A1), hereafter referred to as Kim.
As to claim 1, Kim discloses a display panel (fig 1, DD) having a display region (pixel region including PXA) and a non-display region (peripheral region) surrounding the display region (pixel region), wherein the display panel (DD) comprises a cathode signal trace (UCE) and a cathode layer (EL2), the cathode signal trace comprises a first race part (UCE), and the first trace part is located in the display region (fig 2, UCE in the pixel region between the pixel PXA); and
the cathode layer (EL2) is located at one side of the cathode signal trace (UCE), covers the display region (pixel region of DD), and is electrically connected to the first trace part (UCE; [0078]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee et al. (US Pub. No. 2005/0236629 A1), hereafter referred to as Lee.
As to claim 2, Kim discloses the display panel of claim 1 (paragraphs above),
wherein the first trace part is implemented as a plurality of first trace parts, part of the plurality of first trace parts are arranged at intervals in a first direction ([0119]).
Kim does not disclose part of the plurality of first trace parts are arranged at intervals in a second direction, and the second direction is different from the first direction.
Nonetheless, Lee discloses a similar display device including similar cathode signal trace (figs 5A-B, 520) wherein a first trace part is implemented as a plurality of first trace parts, part of the plurality of first trace parts are arranged at intervals in a first direction (horizontal) and part of the plurality of first trace parts are arranged at intervals in a second direction (vertical), and the second direction is different from the first direction (vertical is different from horizontal).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to extend the traces of Kim in both the horizontal and vertical directions as taught by Lee since this will further reduce the voltage drop of the cathode contact to the LEDs by decreasing the resistance of the cathode component of the display device.
As to claim 4, Kim in view of Lee disclose the display panel of claim 2 (paragraphs above).
Kim further discloses an anode layer (fig 2, EL1), a pixel definition layer (PDL), a light emitting layer (EML), and a signal transmitting layer (UCE layer), wherein the anode layer (EL1), the pixel definition layer (PDL), the light emitting layer (EML), and the signal transmitting layer (UCE layer) are all located at a same side of the cathode layer (EL2); the anode layer comprises a plurality of anodes (EL1 for ED-1, ED-2, ED-3), the pixel definition layer (PDL) is disposed on one side of the anode layer (EL1) facing towards the cathode layer (EL2), the pixel definition layer defines a plurality of pixel apertures (openings of PDL), and each of the plurality of pixel apertures extends through the pixel definition layer in a thickness direction of the pixel definition layer and exposes one of the plurality of anodes (openings in PDL expose EL1); the light emitting layer comprises a plurality of display pixels (EML-1, EML-2, EML-3), and each of the plurality of display pixels is disposed in one of the plurality of pixel apertures (apertures of PDL); and the signal transmitting layer (UCE layer) is disposed on a surface of the pixel definition layer (PDL) away from the anode layer (EL1), the signal transmitting layer (UCE layer) comprises the plurality of first trace parts (UCE extending in first direction), two adjacent first trace parts (UCE traces) are respectively located at two opposite sides of at least one anode (EL1), and the cathode layer (EL2) covers the pixel definition layer (PDL), the light emitting layer (EML), and the signal transmitting layer (UCE layer).
Claim(s) 3 and 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Wang et al. (US Pub. No. 2024/0407217 A1), hereafter referred to as Wang.
As to claim 3, Kim discloses the display panel of claim 1 (paragraphs above).
Kim does not disclose wherein the cathode signal trace further comprises a second trace part, and the second trace part is located in the non-display region, surrounds the display region, and is electrically connected to both the first trace part and the cathode layer.
Nonetheless, Wang discloses wherein a cathode signal trace (figs 2-3, trace 2; [0106]) comprises a second trace part (22), and the second trace part (22) is located in a non-display region (AN), surrounds the display region (AA), and is electrically connected to both a first trace part (21) and the cathode layer (33).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the cathode signal trace part in the non-display region that surrounds the display region of Kim as taught by Wang since this will greatly reduce the resistance of the signal line (Wang, [0106]).
As to claim 12, Kim discloses a display device (fig 1, DD), comprising:
a display panel (DD);
wherein the display panel has a display region (pixel region) and a non-display region (peripheral region) surrounding the display region (pixel region), the display panel comprises a cathode signal trace (UCE) and a cathode layer (EL2), the cathode signal trace comprises a first trace part (UCE), and the first trace part is located in the display region (pixel region); and
the cathode layer (EL2) is located at one side of the cathode signal trace (UCE), covers the display region (pixel region), and is electrically connected to the first trace part (UCE; [0078]).
Kim does not explicitly disclose wherein the display device includes a display terminal comprising a housing and a display panel mounted on the housing.
Nonetheless, Wang discloses a display device including a display terminal comprising a housing and a display panel mounted on the housing ([0131]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the display panel of Kim in a display terminal comprising a housing with the display panel mounted on the housing as taught by Wang since this apparatus increases the functionality of the display by incorporation in a terminal device.
As to claim 13, Kim in view of Wang disclose the display terminal of claim 12 (paragraphs above).
Kim further discloses wherein the first trace part is implemented as a plurality of first trace parts, part of the plurality of first trace parts are arranged at intervals in a first direction ([0119]).
Kim does not disclose part of the plurality of first trace parts are arranged at intervals in a second direction, and the second direction is different from the first direction.
Nonetheless, Wang discloses a similar display device including similar cathode signal trace (fig 3, 2) wherein a first trace part (21) is implemented as a plurality of first trace parts, part of the plurality of first trace parts are arranged at intervals in a first direction (horizontal) and part of the plurality of first trace parts are arranged at intervals in a second direction (vertical), and the second direction is different from the first direction (vertical is different from horizontal).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to extend the traces of Kim in both the horizontal and vertical directions as taught by Wang since this will further reduce the voltage drop of the cathode contact to the LEDs by decreasing the resistance of the cathode component of the display device.
As to claim 14, Kim in view of Wang disclose the display terminal of claim 12 (paragraphs above).
Kim does not disclose wherein the cathode signal trace further comprises a second trace part, and the second trace part is located in the non-display region, surrounds the display region, and is electrically connected to both the first trace part and the cathode layer.
Nonetheless, Wang discloses wherein a cathode signal trace (figs 2-3, trace 2; [0106]) comprises a second trace part (22), and the second trace part (22) is located in a non-display region (AN), surrounds the display region (AA), and is electrically connected to both a first trace part (21) and the cathode layer (33).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the cathode signal trace part in the non-display region that surrounds the display region of Kim as taught by Wang since this will greatly reduce the resistance of the signal line (Wang, [0106]).
As to claim 15, Kim in view of Wang disclose the display terminal of claim 13 (paragraphs above).
Kim further discloses wherein the display panel (fig 2) further comprises: an anode layer (fig 2, EL1), a pixel definition layer (PDL), a light emitting layer (EML), and a signal transmitting layer (UCE layer), wherein the anode layer (EL1), the pixel definition layer (PDL), the light emitting layer (EML), and the signal transmitting layer (UCE layer) are all located at a same side of the cathode layer (EL2); the anode layer comprises a plurality of anodes (EL1 for ED-1, ED-2, ED-3), the pixel definition layer (PDL) is disposed on one side of the anode layer (EL1) facing towards the cathode layer (EL2), the pixel definition layer defines a plurality of pixel apertures (openings of PDL), and each of the plurality of pixel apertures extends through the pixel definition layer in a thickness direction of the pixel definition layer and exposes one of the plurality of anodes (openings in PDL expose EL1); the light emitting layer comprises a plurality of display pixels (EML-1, EML-2, EML-3), and each of the plurality of display pixels is disposed in one of the plurality of pixel apertures (apertures of PDL); and the signal transmitting layer (UCE layer) is disposed on a surface of the pixel definition layer (PDL) away from the anode layer (EL1), the signal transmitting layer (UCE layer) comprises the plurality of first trace parts (UCE extending in first direction), two adjacent first trace parts (UCE traces) are respectively located at two opposite sides of at least one anode (EL1), and the cathode layer (EL2) covers the pixel definition layer (PDL), the light emitting layer (EML), and the signal transmitting layer (UCE layer).
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2019/0326376A1 and US Pub. No. 2022/0310740A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 4/16/2026
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