DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of “Invention Group II (Claims 17-20)” and new Claims 21-36 in the reply filed on 04/06/2026, is acknowledged.
Claims 1-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17,23,29-30 and 36 are rejected under 35 U.S.C. 103 as being obvious over US 2023/0268403 A1; Chuang et al.; 08/2023; (“403”).
Regarding Claim 17. 403 teaches in Fig. 2J about a semiconductor device, comprising:
a dielectric liner (item 212) lining shallow trench isolation regions (item 212 is lining item regions 218);
contacts (items 220) formed through and in contact with the dielectric liner (items 220 are formed through and in contact with liner item 212);
wherein the contacts include a straight profile through the dielectric liner lining the shallow trench isolation regions (contact items 220 include a straight profile through items 212 and 218).
403 does not teach about a semiconductor device, comprising:
an inner spacing layer;
an interlevel dielectric layer in contact with the inner spacing layer; and
contacts formed through the interlevel dielectric layer and through the inner spacing layer;
wherein the contacts include a straight profile through the interlevel dielectric layer as delineated by inner spacers formed within the inner spacing layer and within the straight profile.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to place together various nonconductive elements to form a nonconductive vertically extended shallow trench isolation region and its respective dielectric liner delineating straight profile contacts (especially when the nonconductive elements, as a whole, maintain the overall profile of the formerly integral structure), since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. In re Dulberg, 129 USPQ 348, 349 (CCPA 1961). See MPEP 2144.04.
Regarding Claim 23. 403 teaches in Fig. 2J about a semiconductor device, comprising:
a dielectric liner (item 212) lining shallow trench isolation regions (item 212 is lining item regions 218);
contacts (items 220) formed through and in contact with the dielectric liner (items 220 are formed through and in contact with liner item 212);
403 does not teach about a semiconductor device, comprising:
an inner spacing layer;
an interlevel dielectric layer in contact with the inner spacing layer;
contacts formed through the interlevel dielectric layer and through the inner spacing layer; and
inner spacers formed within the inner spacing layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to place together various nonconductive elements to form a nonconductive vertically extended shallow trench isolation region and its respective dielectric liner (especially when the nonconductive elements, as a whole, maintain the overall profile of the formerly integral structure, as shown in the figures of the present application), since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. In re Dulberg, 129 USPQ 348, 349 (CCPA 1961). See MPEP 2144.04.
Regarding Claim 29. 403 teaches in Fig. 2J about a semiconductor device, wherein the contacts include a straight profile through the dielectric liner lining the shallow trench isolation regions (contact items 220 include a straight profile through items 212 and 218).
403 does not teach about a semiconductor device, wherein the contacts include a straight profile through the interlevel dielectric layer as delineated by the inner spacers formed within the inner spacing layer and within the straight profile.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to place together various nonconductive elements to form a nonconductive vertically extended shallow trench isolation region and its respective dielectric liner delineating straight profile contacts (especially when the nonconductive elements, as a whole, maintain the overall profile of the formerly integral structure), since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. In re Dulberg, 129 USPQ 348, 349 (CCPA 1961). See MPEP 2144.04.
Regarding Claim 30. 403 teaches in Fig. 2J about a semiconductor device, comprising:
a dielectric liner (item 212);
contacts (items 220) formed through and in contact with the dielectric liner (items 220 are formed through and in contact with liner item 212);
wherein the contacts include a straight profile through the dielectric liner (contact items 220 include a straight profile through item 212).
403 does not teach about a semiconductor device, comprising:
an inner spacing layer;
an interlevel dielectric layer in contact with the inner spacing layer; and
contacts formed through the interlevel dielectric layer and through the inner spacing layer;
wherein the contacts include a straight profile through the interlevel dielectric layer as delineated by inner spacers formed within the inner spacing layer and within the straight profile.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to place together various nonconductive elements to form a nonconductive vertically extended dielectric liner delineating straight profile contacts (especially when the nonconductive elements, as a whole, maintain the overall profile and fill of the formerly integral structure), since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. In re Dulberg, 129 USPQ 348, 349 (CCPA 1961). See MPEP 2144.04.
Regarding Claim 36. 403 teaches in Fig. 2J about a semiconductor device, wherein the dielectric liner (item 212) lining shallow trench isolation regions (item 212 is lining item regions 218).
Allowable Subject Matter
Claims 18-22,24-28 and 31-35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
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