DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 11/16/2023 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation "a pattern insulating layer" in line. There is already “a pattern insulating layer” introduced in claim 11, on which claim 17 depends, referred to as “the pattern insulating layer” thereafter – rendering it unclear if “a pattern insulating layer” in claim 17 refers to the same or a different ‘pattern insulating layer’. Therefore, for Examination purposes, “a pattern insulating layer” in claim 17 has been interpreted as --- the pattern insulating layer --- however, this edit may be altered if Applicant intends otherwise.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-14, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noh (U.S. PG Pub No US2021/0193678A1).
Regarding claim 1, Noh teaches a semiconductor device (100) figs. 2, 3A-3B [0022] comprising:
a substrate (10) figs. 3A-3B [0026] comprising (hosting) a chip region (CA in boxed area) fig. 2 [0024] and a scribe lane region (SLR) [see annotated fig. 2 below] around the chip region (CA) and comprising a first key pattern region (KPR1) [see annotated figs. 2, 3B below];
a capping insulating layer (34) fig. 3B [0027] disposed on the (in/on bottom area of) scribe lane region (SLR comprising KPR1, KPR2);
a barrier metal layer (40) fig. 3B [0029] covering (bordering) the (top of) capping insulating layer (34) and an inner wall (sidewall) of a via hole (VH = opening in 34, 40, 42, 44 filled by 32, 46, 170 material) fig. 3B [0027-0028, 0034] (see annotated fig. 3B below) penetrating the capping insulating layer (34);
a substrate layer (170-silicon-material) fig. 3B [0071] disposed on the (supported by sidewall of) barrier metal layer (40) and (partially) filling the via hole (VH);
an insulating plate (upper 42a) fig. 3B [0052] and an upper base layer (44) fig. 3B [0029] sequentially disposed on (supported by sidewalls of) the substrate layer (170);
a pattern insulating layer (comprising lower 42a with 46) fig. 3B [0028] disposed on the capping insulating layer (34) in the first key pattern region (KPR1);
a stacked structure (110 comprising 112, WL1) fig. 3B [0030] disposed on the upper base layer (44) and the pattern insulating layer (lower 42a with 46); and
a plurality of first pattern structures (DCS’s in KPR1) fig. 3B [0028] overlapping the pattern insulating layer (comprising lower 42a) in a vertical direction and penetrating the stacked structure and a part of the pattern insulating layer, wherein the pattern insulating layer (comprising 46) extends through the barrier metal layer (40) in the first key pattern region (KPR1) in a vertical direction (see annotated figs. 2 and 3B below).
[AltContent: arrow][AltContent: arrow][AltContent: textbox (KPR2)][AltContent: textbox (KPR1)][AltContent: rect][AltContent: rect][AltContent: textbox (Chip/memory cell region (CA) in boxed area)][AltContent: arrow][AltContent: textbox (Scribe lane region (SLR) in dashed area)][AltContent: arrow][AltContent: rect][AltContent: rect][AltContent: rect][AltContent: rect][AltContent: rect]
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Annotated fig. 2 of Noh
[AltContent: connector][AltContent: arrow][AltContent: textbox (VL2)][AltContent: arrow][AltContent: arrow][AltContent: textbox (HA2)][AltContent: arrow][AltContent: rect][AltContent: textbox (HA1)][AltContent: rect][AltContent: textbox (VL1)][AltContent: connector][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (KPR2)][AltContent: textbox (KPR1)][AltContent: rect][AltContent: rect][AltContent: textbox (VH)][AltContent: ]
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Annotated fig. 3B of Noh
Regarding claim 2, Noh teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim 1. Noh also teaches wherein an upper surface (uppermost surface of 46) of the pattern insulating layer (comprising lower 42a with 46) fig. 3B [0028] is positioned at a same vertical level as an upper (uppermost) surface of the upper base layer (44) fig. 3B [0029].
Regarding claim 3, Noh teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim 1. Noh also teaches wherein a lower surface (lowermost surface of 46) of the pattern insulating layer (comprising lower 42a with 46) fig. 3B [0028] is positioned at a same vertical level as an upper (uppermost) surface of the capping insulating layer (34) fig. 3B [0027].
Regarding claim 4, Noh teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim 1. Noh also teaches wherein the scribe lane region (SLR) [see annotated figs. 2, 3B above] further includes a second key pattern region (KPR2) [see annotated figs. 2, 3B above], and a plurality of second pattern structures (DCS’s in KPR2) fig. 3B [0028] are disposed in the second key pattern region (KPR2).
Regarding claim 5, Noh teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim 4. Noh also teaches wherein the pattern insulating layer (comprising lower 42a with 46) fig. 3B [0028] is not disposed in the second key pattern region (KPR2, as defined in annotated figs. 2, 3B above].
Regarding claim 6, Noh teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim 4. Noh also teaches wherein a horizontal area (HA1) and a vertical length (VL1) of each of the plurality of first pattern structures (DCS’s in KPR1) fig. 3B [0028] (defined based on entire DCS structure) are greater than a horizontal area (HA2) and a vertical length (VL2) of each of the plurality of second pattern structures (DCS’s in KPR2) fig. 3B [0028] (defined based on 152-insulating-fill of DCS, see fig. 4) [as defined in annotated figs. 2, 3B above].
Regarding claim 9, Noh teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim 1. Noh also teaches wherein each of the first pattern structures (DCS’s in KPR1) fig. 3B [0028] includes a plurality of insulating layers (140 comprising 142, 144, 146) fig. 4 [0039] and a channel layer (150) fig. 4 [0039] sequentially formed on an inner wall of a first pattern channel hole (gap in 116, 136 filled by DCS) positioned in the stacked structure (110 comprising 112, WL1) fig. 3B [0030] and the pattern insulating layer (comprising lower 42a with 46) fig. 3B [0028].
Regarding claim 10, Noh teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim 9. Noh also teaches wherein the plurality of insulating layers (comprising 142, 144, 146) fig. 4 [0039] form an oxide-nitride-oxide (ONO) structure (silicon oxide – silicon nitride – silicon oxide, respectively [0039]).
Regarding claim 11, Noh teaches a semiconductor device (100) figs. 2, 3A-3B [0022] comprising:
a substrate (10) figs. 3A-3B [0026] comprising (hosting) a chip region (spacer comprising entirety of 100) comprising a memory cell region (CA) fig. 3A [0024] and a connection region (KPR1 and KPR2);
a capping insulating layer (34) fig. 3B [0027] disposed (in/on bottom area of) on the chip region (100);
a barrier metal layer (40) fig. 3B [0029] covering (bordering) the (top of) capping insulating layer (34) and an inner wall (sidewall) of a via hole (VH = opening in 34, 40, 42, 44 filled by 32, 46, 170 material) fig. 3B [0027-0028, 0034] (see annotated fig. 3B below) penetrating the capping insulating layer (34);
a substrate layer (170-silicon-material) fig. 3B [0071] disposed on the barrier metal layer (40) and (partially) filling the via hole (VH);
a lower base layer (43) fig. 3A [0028] disposed on (supported by) the substrate layer (170) in the memory cell region (CA) fig. 3A [0024] and an insulating plate (upper 42a) fig. 3B [0052] disposed on (supported by) the substrate layer (170) in the connection region (KRP1 and KRP2);
an upper base layer (44) figs. 3A, 3B [0029] disposed on the lower base layer (43) and the insulating plate (upper 42a);
a pattern insulating layer (comprising lower 42a with 46) fig. 3B [0028] disposed on the capping insulating layer (34) in a partial region of the connection region (KRP1 and KRP2);
a stacked structure (110 comprising 112, WL1) fig. 3B [0030] disposed on (supported by) the pattern insulating layer (comprising lower 42a with 46) and the upper base layer (44); and
a plurality of dummy channel structures (DCS’s) fig. 3B [0028] overlapping the pattern insulating layer (comprising lower 42a with 46) in a vertical direction and penetrating the stacked structure (110) and a part (lower 42a portion) of the pattern insulating layer (lower 42a, 46), wherein the pattern insulating layer (comprising 46 with 42a) extends through the barrier metal layer (40) in the connection region (comprising KPR1) in a vertical direction.
[AltContent: textbox (Memory cell region (CA) in boxed area)][AltContent: arrow][AltContent: arrow][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: textbox (KPR2)][AltContent: textbox (KPR1)][AltContent: rect][AltContent: rect][AltContent: arrow][AltContent: textbox (Chip Region (CR) in dashed area)][AltContent: arrow][AltContent: rect][AltContent: rect]
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Annotated fig. 2 of Noh
[AltContent: rect][AltContent: connector][AltContent: arrow][AltContent: textbox (VL2)][AltContent: arrow][AltContent: arrow][AltContent: textbox (HA2)][AltContent: arrow][AltContent: rect][AltContent: textbox (HA1)][AltContent: textbox (VL1)][AltContent: connector][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (KPR2)][AltContent: textbox (KPR1)][AltContent: rect][AltContent: rect][AltContent: textbox (VH)][AltContent: ]
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Annotated fig. 3B of Noh
Regarding claim 12, Noh teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim1 1. Noh also teaches wherein an upper surface (uppermost surface of 46) of the pattern insulating layer (comprising lower 42a with 46) fig. 3B [0028] is positioned at a same vertical level as an upper (uppermost) surface of the upper base layer (44) fig. 3B [0029].
Regarding claim 13, Noh teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim 1. Noh also teaches wherein a lower surface (lowermost surface of 46) of the pattern insulating layer (comprising lower 42a with 46) fig. 3B [0028] is positioned at a same vertical level as an upper (uppermost) surface of the capping insulating layer (34) fig. 3B [0027].
Regarding claim 14, Noh teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim 11. Noh also teaches further comprising:
a plurality of channel structures (CS) fig. 3A [0028] disposed on the memory cell region (CA) fig. 3A [0024], wherein a horizontal area (HA1) and a vertical length (VL1) of each of the plurality of dummy channel structures (DCS’s in KPR1) fig. 3B [0028] are greater than a horizontal area (HA2) and a vertical length (VL2) of each of the plurality of channel structures (defined based on 152-insulating-fill of DCS/CS, see fig. 4) (DCS may have substantially the same structure as CS [0039], hence right DCS in KRP2 of fig. 3B is used to for exemplary size comparison) [as defined in annotated figs. 2, 3B above].
Regarding claim 17, Noh teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim 11. Noh also teaches wherein the pattern insulating layer (comprising lower 42a with 46) fig. 3B [0028] is (entirely) not disposed in the memory cell region (CA) fig. 3A [0024].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7-8, 15-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Noh (U.S. PG Pub No US2021/0193678A1) in view of Kim (U.S. PG Pub No US2021/0066276A1).
Regarding claim 7, Noh teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim 1. Noh also teaches wherein each of the first pattern structures (DCS’s in KPR1) fig. 3B [0028] includes a first metal layer (154) fig. 3B, fig. 4 [0064] disposed on (bordering) an inner wall of a first pattern channel hole (opening hosting DCS) positioned in the stacked structure (110 comprising 112, WL1) fig. 3B [0030] and the pattern insulating layer (comprising lower 42a with 46) fig. 3B [0028].
However, Noh does not explicitly disclose wherein each of the first pattern structures (DCS’s in KPR1) fig. 3B [0028] includes a first barrier layer and a first metal layer (154) sequentially disposed on (bordering) an inner wall of a first pattern channel hole (opening hosting DCS).
Kim teaches a semiconductor memory device (400a) fig. 6 [0058-0059] wherein each of the first pattern structures (comprising 130 with 142 with BL) fig. 4B [0052-0053] includes a first barrier layer (BL) fig. 4B [0052, 0054] and a first metal layer (142) fig. 4B [0053] sequentially (sequentially from top to bottom) disposed on (bordering) an inner wall of a first pattern channel hole (hole comprising 130 with 142 with BL) fig. 4B [0052-0054].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the channel/dummy channel structures of Noh to comprise an additional conductive layer at an upper region of the channel hole [0052-0054] atop the conductive pad [0054] in order to enhance electrical connectivity with underlying memory structures [0052-0054] and external circuitry [0053], thereby increasing the integration degree of memory components and reducing chip size [0004], as taught by Kim.
Regarding claim 8, Noh in view of Kim teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim 7. Noh in view of Kim (with reference to Kim) also teaches wherein the first barrier layer (BL) fig. 4B [0052] includes TiN [0054] and the first metal layer (142) fig. 4B [0053] includes any one of tungsten, tantalum, tungsten nitride, titanium nitride, tantalum nitride, or a combination thereof [0054].
Regarding claim 15, Noh teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim 11. Noh also teaches wherein the capping insulating layer (comprising 34 with 12) fig. 3B [0025, 0051] includes a first capping insulating layer (34) and a second capping insulating layer (12) disposed on (bottom of) the first capping insulating layer (34).
However, Noh does not explicitly disclose and the second capping insulating layer (12) and the pattern insulating layer (34) include a same material (12 may comprise silicon oxide [0051], however, material of 34 not explicitly disclosed).
Kim teaches a semiconductor memory device (400a) fig. 6 [0058-0059] wherein the pattern insulating layer (290) fig. 6 [0067] includes silicon oxide [0067] (rendering it the same composition as layer 12 of Noh).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peripheral interlayer insulating film of Noh hosting transistor circuitry [0067, 0065] to explicitly be composed of silicon oxide [0067], the same material as the second capping layer 12 of Noh [0051 Noh], because the silicon oxide’s art recognized suitability for use insulating circuitry components [0065-0068], as evidenced by Kim.
Regarding claim 16, Noh teaches the semiconductor device (100) figs. 2, 3A-3B [0022] of claim 15. Noh also teaches wherein the second capping insulating layer (12) fig. 3B [0025, 0051] and the pattern insulating layer (comprising lower 42a) fig. 3B [0028] include silicon oxide [0051-0052].
Regarding claim 18, Noh teaches an electronic system (100) figs. 2, 3A-3B [0022] comprising:
a main substrate (comprising 162) figs. 3A-3B [0033];
a semiconductor device (comprising components of 100 underlying 162) figs. 3A-3B [0022] on the (bottom of) main substrate (162);
wherein the semiconductor device (comprising components of 100 underlying 162) includes:
a substrate (10) figs. 3A-3B [0026] comprising (hosting) a chip region (CA in boxed area) fig. 2 [0024] and a scribe lane region (SLR) [see annotated fig. 2 below] around the chip region (CA) and comprising a first key pattern region (KPR1) [see annotated figs. 2, 3B below];
a capping insulating layer (34) fig. 3B [0027] disposed on the (in/on bottom area of) scribe lane region (SLR comprising KPR1, KPR2);
a barrier metal layer (40) fig. 3B [0029] covering (bordering) the (top of) capping insulating layer (34) and an inner wall (sidewall) of a via hole (VH = opening in 34, 40, 42, 44 filled by 32, 46, 170 material) fig. 3B [0027-0028, 0034] (see annotated fig. 3B below) penetrating the capping insulating layer (34);
a substrate layer (170-silicon-material) fig. 3B [0071] disposed on the (supported by sidewall of) barrier metal layer (40) and (partially) filling the via hole (VH);
an insulating plate (upper 42a) fig. 3B [0052] and an upper base layer (44) fig. 3B [0029] sequentially disposed on (supported by sidewalls of) the substrate layer (170);
a pattern insulating layer (comprising lower 42a with 46) fig. 3B [0028] disposed on the capping insulating layer (34) in the first key pattern region (KPR1);
a stacked structure (110 comprising 112, WL1) fig. 3B [0030] disposed on the upper base layer (44) and the pattern insulating layer (lower 42a with 46); and
a plurality of first pattern structures (DCS’s in KPR1) fig. 3B [0028] overlapping the pattern insulating layer (comprising lower 42a) in a vertical direction and penetrating the stacked structure and a part of the pattern insulating layer, wherein the pattern insulating layer (comprising 46) extends through the barrier metal layer (40) in the first key pattern region (KPR1) in a vertical direction (see annotated figs. 2 and 3B below).
[AltContent: rect][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: textbox (KPR2)][AltContent: textbox (KPR1)][AltContent: rect][AltContent: textbox (Chip/memory cell region in boxed area)][AltContent: arrow][AltContent: textbox (Scribe lane region (SLR) in dashed area)][AltContent: arrow][AltContent: rect][AltContent: rect][AltContent: rect][AltContent: rect]
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Annotated fig. 2 of Noh
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Annotated fig. 3B of Noh
However, Noh does not explicitly disclose and a controller electrically connected to the semiconductor device (comprising components of 100 underlying 162) on the main substrate (162).
Kim teaches a semiconductor memory device (20) fig. 4A [0024] comprising a controller (not shown; connected to memory area 20) fig. 4A [0028-0030] electrically connected to the semiconductor device (comprising 20) on the main substrate (145) fig. 4B [0053].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory cell array circuitry of Noh to comprise the memory controller of Kim in order to facilitate the efficient transfer of memory data for reading and writing memory operations [0028, 0030], thereby increasing the integration degree of memory components and reducing chip size [0004], as taught by Kim.
Regarding claim 19, Noh in view of Kim teaches the electronic system (100) figs. 2, 3A-3B [0022] of claim 18. Noh also teaches wherein a lower surface (lowermost surface of 46) of the pattern insulating layer (comprising lower 42a with 46) fig. 3B [0028] is positioned at a same vertical level as an upper (uppermost) surface of the capping insulating layer (34) fig. 3B [0027].
Regarding claim 20, Noh in view of Kim teaches the electronic system (100) figs. 2, 3A-3B [0022] of claim 18. Noh also teaches wherein the chip region (CA) fig. 3A [0024] of the substrate includes a memory cell region (CA) fig. 2 [0024] and a connection region (entirety of space comprising 100 is interconnected, connection region coexists in CA and SLR), and the semiconductor device (100) further includes a second pattern insulating layer (140s of DCS’s in KPR2) fig. 3B, fig. 4 [0028, 0039] disposed on (supported by) the capping insulating layer (34) fig. 3B [0027] in the connection region (entirety of space comprising 100); and
a plurality of dummy channel structures (150, 152’s of DCS’s in KPR2) fig. 3B, fig. 4 [0028, 0039] overlapping the second pattern insulating layer (140s of DCS’s in KPR2) in a vertical direction and penetrating (passing through) a part of the second pattern insulating layer (140s of DCS’s in KPR2) and the stacked structure (110 comprising 112, WL1) fig. 3B [0030], and wherein the second pattern insulating layer (140s of DCS’s in KPR2) extends through the barrier metal layer (40) fig. 3B [0029] in the connection region (entirety of space comprising 100) in a vertical direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
All references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature 3-D memory devices with pattern structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 01/17/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892