Prosecution Insights
Last updated: April 19, 2026
Application No. 18/511,432

METHOD OF MANUFACTURING METHOD A SEMICONDUCTOR DEVICE, A SEMICONDUCTOR DEVICE MANUFACTURED USING THIS METHOD AND A MOSFET DEVICE MANUFACTURED ACCORDING TO THE METHOD

Non-Final OA §102§112
Filed
Nov 16, 2023
Examiner
HENRY, CALEB E
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nexperia B V
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
93%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
1052 granted / 1217 resolved
+18.4% vs TC avg
Moderate +6% lift
Without
With
+6.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
48 currently pending
Career history
1265
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
49.8%
+9.8% vs TC avg
§102
36.3%
-3.7% vs TC avg
§112
11.2%
-28.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1217 resolved cases

Office Action

§102 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 1-15 and 19 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 1/7/2025. After reviewing Applicant’s arguments, it is determined that the inventions mentioned in Restriction Requirement, filed 1/7/2026, should be examined separately for reasons outlined in Restriction Requirement, filed 1/7/2026, namely distinctness of inventions (as exemplified in independent claims 1 and 16), as well as undue search burden that would be endured if both inventions were examined together (claims 1 and 16 being classified separately, as shown in Restriction Requirement, filed 1/7/2026). For at least this reason, elected claims 16-18 will be examined and claims 1-15 and 19 will be withdrawn. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 16 recites the limitation "the liner oxide layer". There is insufficient antecedent basis for this limitation in the claim. Claim 16 recites the limitation "the gate oxide layer". There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 16-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bobde (20230238440) . PNG media_image1.png 388 344 media_image1.png Greyscale Regarding claim 16, Bobde teaches a trench-gate semiconductor device (please see figure above) comprising a trench (please see fig. 5J which shows the totality of the two trenches) that when seen in a vertical direction from a top layer side towards a bottom layer side of a single epitaxial (EPI) layer (502; par. 26 teaches 502 being an epi layer), is divided into a first trench (please see top trench in fig. 5J) having a depth formed from the top layer side towards a first trench bottom and a second trench (please see bottom trench in fig. 5J) having a depth formed from the first trench bottom towards the bottom layer side (please see above), further comprising a source poly (105; par. 20 teaches 105 is coupled to the source voltage and is made of poly) arranged in the second trench and a gate poly (106; par. 19 teaches a gate made of poly) arranged in the first trench and separated from the source poly by a inter poly oxide layer, wherein the second trench has a width that is larger than the width of the first trench (please see trench widths in fig. 5J) and the depth of the second trench is larger than the depth of the first trench (par. 33 teaches widening and deepening the bottom trench seen in 5J, when compared to the top trench) and the liner oxide layer (please see 112 rejection above) is thicker than the gate oxide layer (please see 112 rejection above). Regarding claim 17, Bobde teaches a trench-gate semiconductor device according to claim 16, wherein the first trench width to the second trench width ratio is in a range from 1:1.7 to 1:2 (par. 28, 30 and 33). Regarding claim 18, Bobde teaches a trench-gate semiconductor device according to claim 16, wherein 18. source poly width to gate poly width ratio is in a range from 0.7:1 to 1.2:1 (par. 28, 30 and 33). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CALEB E HENRY/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Nov 16, 2023
Application Filed
Feb 27, 2026
Non-Final Rejection — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 5m to grant Granted Apr 14, 2026
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
93%
With Interview (+6.2%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 1217 resolved cases by this examiner. Grant probability derived from career allow rate.

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