Prosecution Insights
Last updated: July 17, 2026
Application No. 18/511,535

SEMICONDUCTOR DEVICE

Non-Final OA §102§103§112
Filed
Nov 16, 2023
Priority
Nov 17, 2022 — JP 2022-183959
Examiner
MIYOSHI, JESSE Y
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Renesas Electronics Corporation
OA Round
1 (Non-Final)
57%
Grant Probability
Moderate
1-2
OA Rounds
11m
Est. Remaining
76%
With Interview

Examiner Intelligence

Grants 57% of resolved cases
57%
Career Allowance Rate
276 granted / 484 resolved
-11.0% vs TC avg
Strong +19% interview lift
Without
With
+18.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
30 currently pending
Career history
541
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
75.6%
+35.6% vs TC avg
§102
16.0%
-24.0% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 484 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of device embodiment 3 as shown in fig. 12 (claims 1-9, 11, 12 readable thereon, claim 10 withdrawn) in the reply filed on 4/9/2026 is acknowledged. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 3 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The original specification as filed lacks description as to how the first well WL1 is in a floating state because WL1 is directly connected to the substrate material SU. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 5-7, 10-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites “the trench and the dielectric film are disposed in a region under between the two electric fuse cells of the plurality of electric fuse cells next to each other” at lines 3-4. It is unclear as to what is meant by the term “under between” since the trench and dielectric are as a level under the fuse cells, they are not between fuse cells. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 2, and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai et al. (PGPub 2015/0001592; hereinafter “Lai”). Re claim 1: Lai teaches (e.g. figs. 3A,B, 6C) a semiconductor device comprising: a semiconductor substrate (substrate 302; e.g. paragraph 21); a dielectric film (passivation 324; e.g. paragraph 21) disposed on the semiconductor substrate (302); a plurality of electric fuse portions (metal fuse portions 320a, 320b and multiple levels 628, 629 as shown in fig. 6C; e.g. paragraphs 21, 22) disposed on the dielectric film (324); and a first well region (active region 352; e.g. paragraph 21) of a first conductivity type (352 is a doped well of either n or p type as shown in fig. 6c) disposed in the semiconductor substrate (302) and on a surface of the semiconductor substrate (302), wherein the first well region (352) is configured by integrally connecting a well region (region of 352 under 320a, 320b, 628, 629) located under each of the plurality of electric fuse portions (320a, 320b, 628, 629) to each other. Re claim 2: Lai teaches the semiconductor device according to claim 1, wherein each of a plurality of electric fuse cells (628, 629) is configured by one of the plurality of electric fuse portions (320a, 320b, 628, 629) and a pair of pad portions (318, 319) connected to both ends of the one of the plurality of electric fuse portions (320a, 320b, 628, 629), and wherein the first well region (352) is disposed in a region under a region sandwiched between two electric fuse cells (628, 629) of the plurality of electric fuse cells next to each other (628, 629 are next to each other). Re claim 4: Lai teaches the semiconductor device according to claim 2, wherein the semiconductor substrate (302) has a trench (trench for 350; hereinafter “T”), and wherein the dielectric film (isolation region 350; e.g. paragraph 21) fills the trench (T). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai as applied to claims 1 above, and further in view of Allman et al. (US PGPub 2021/0104460; hereinafter “Allman”). Re claim 8: Lai teaches substantially the entire device as claimed in claim 1 except explicitly teaching wherein each of the plurality of electric fuse portions includes a polysilicon layer and a silicide layer in contact with the polysilicon layer. Allman teaches (e.g. fig. 3) each of the plurality of electric fuse portions (fuse 21; e.g. paragraph 27) includes a polysilicon layer (polysilicon 221; e.g. paragraph 27) and a silicide layer (silicide 222; e.g. paragraph 27) in contact with the polysilicon layer (221). It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the fuse structure as taught by Allman in the device of Lai in order to have the predictable result of simplifying manufacture and design using a known structure for fuse devices. Re claim 9: Lai teaches substantially the entire device as claimed in claim 1 except explicitly teaching the semiconductor device comprising: a substrate region of the second conductivity type is disposed in the semiconductor substrate and forming a pn junction with the first well region. Allman teaches (e.g. fig. 3) a substrate region (14) of the second conductivity type (14 is P-type; e.g. paragraph 37) is disposed in the semiconductor substrate (14) and forming a pn junction with the first well region (well region 41 is opposite conductivity type as 14; e.g. paragraph 37). It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the fuse structure as taught by Allman in the device of Lai in order to have the predictable result of using the well region to help contain and electrically isolate cracks from within the fuse structure from the substrate (see paragraph 38 of Allman). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JESSE Y MIYOSHI/ Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Nov 16, 2023
Application Filed
May 13, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
57%
Grant Probability
76%
With Interview (+18.7%)
3y 7m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 484 resolved cases by this examiner. Grant probability derived from career allowance rate.

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