Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION This office action is in response to the application filed on 11/16/2023 . Currently, claims 1-16 are pending in the application. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-16 are rejected under 35 U.S.C. 103 as being obvious over KUWAJIMA (US 20170148732 A1) in view of K aeriyama (US 20120020419 A1) . Regarding claim 1, Figures 1- 4 of KUWAJIMA disclose a n electronic device comprising: a first semiconductor device including a first semiconductor chip (RG2, [0063]) ; and a second semiconductor device (RG1, [0063]) including a second semiconductor chip, wherein the first semiconductor chip (RG2) includes a first isolator (TR1, [0064]) performing non-contact communication between a first potential (at CL11) and a second potential (at CL12) ([0063]-[0064]) , wherein the second semiconductor chip (RG1) includes a second isolator (TR2) performing non-contact communication between a third potential (at CL21 , [0065] ) and a fourth potential (CL22) , wherein a difference between the first potential and the second potential is greater than a difference between the third potential and the fourth potential ([0070]-[0072]) , wherein the first isolator is configured by a first transformer (TR1) or a first capacitor, wherein the second isolator is configured by a second transformer (TR2) or a second capacitor ([0063]-[0064] , transformer in this case ) , wherein the first transformer (TR1 , Figure 1/3 ) includes: a first lower inductor (CL12) ; a first upper inductor (CL11) ; and a first insulating layer (IL3+IL4+IL5, Figure 3) interposed between the lower inductor and the upper inductor, wherein the second transformer (TR2 , Figure 1/4 ) includes: a second lower inductor (CL22) ; a second upper inductor (CL21) ; and a second insulating layer (IL3+IL4+IL5, Figure 4) interposed between the second lower inductor and the second upper inductor ; KUWAJIMA does not explicitly teach wherein a second distance between the second lower inductor and the second upper inductor is smaller than a first distance between the first lower inductor and the first upper inductor . However, KUWAJIMA teaches that the distance between the primary coil and the secondary coil determines the breakdown voltage in the transformer by having thickness of the insulating layer ([0199]), wherein by changing the distance and sizes provides different region to be operated differently in terms of voltage and current with improved performance ([0206] of KUWAJIMA ). Thus , it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the first transformer and the second transformer wherein a second distance between the second lower inductor and the second upper inductor is smaller than a first distance between the first lower inductor and the first upper inductor as the first device is the high voltage and the second device is low voltage in order to improve the performance and reduce the size of the device and further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233. KUWAJIMA, further, does not explicitly teach wherein the first or the second isolator alternately is configured by a first capacitor and a second capacitor, wherein the first capacitor includes: a first lower electrode; a first upper electrode; and a first capacitive insulating layer interposed between the first lower electrode and the first upper electrode, and wherein the second capacitor includes: a second lower electrode; a second upper electrode; and a second capacitive insulating layer interposed between the second lower electrode and the second upper electrode, and wherein a second electrode distance between the second lower electrode and the second upper electrode is smaller than a first electrode distance between the first lower electrode and the first upper electrode. However, K aeriyama is a pertinent art which teaches a semiconductor device including a first semiconductor substrate and a second semiconductor substrate which communicate with each other through an AC coupling element based on different power supply voltages ([0001]), wherein Figure 1 /8/11 of Kaeriyama teach using transformer s as coupling unit between two semiconductor devices , wherein Figure 19 -20 teach capacit ors as coupling unit, and wherein Figure 20 teaches that the transformers in the mounting example shown in FIG. 8 are replaced with capacitors. The mounting example shown in FIG. 20 includes first capacitors Ca in which the first primary coil L11 and the first secondary coil L12, which constitute the first transformer, are respectively replaced with an electrode Ce1a and an electrode Ce2a; and second capacitors Cb in which the second primary coil L11 and the second secondary coil L12, which constitute the second transformer, are respectively replaced with an electrode Ce1b and an electrode Ce2b. As in the mounting example shown in FIG. 19, each of the first capacitor Ca and the second capacitor Cb has a configuration in which an interlayer insulating film formed between the electrodes is used as a dielectric ([0097]). Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use a first capacitor and a second capacitor instead of a first transformer and the second transformer , wherein a second electrode distance between the second lower electrode and the second upper electrode is smaller than a first electrode distance between the first lower electrode and the first upper electrode in the device of KUWAJIMA according to the teaching of Kaeriyama ([0004]) in order to reduce the size and the cost with an improved performance , and further the court has held that a simple substitution of one known element for another (capacitor instead of transformer for isolation device) to obtain predictable results is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007). Regarding claim 2, Figures 1- 4 of KUWAJIMA disclose that the electronic device according to claim 1, wherein the first semiconductor chip (RG2) includes a first multilayer wiring layer ( M1-M4 , Figure 3 ) , wherein the second semiconductor chip (RG1) includes a second multilayer wiring layer ( M1-M4 , Figure 4 ) , wherein the first lower inductor (CL12) is formed in the first multilayer wiring layer (M1-M4, Figure 3) , wherein the first upper inductor (CL11) is formed on the first multilayer wiring layer, wherein the second lower inductor (CL22) is formed in the second multilayer wiring layer (M1-M4, Figure 4) , wherein the second upper inductor (CL21) is formed on the second multilayer wiring layer . KUWAJIMA does not tech wherein a thickness of the second multilayer wiring layer is smaller than a thickness of the first multilayer wiring layer. However, KUWAJIMA teaches that the distance between the primary coil and the secondary coil determines the breakdown voltage in the transformer by having thickness of the insulating layer ([0199]), wherein by changing the distance and sizes provides different region to be operated differently with improved performance ([0206]). However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to improve the performance and reduce the size and cost of the device , and further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 3, Figures 1- 4 of KUWAJIMA in view of Kaeriyama teach that the electronic device according to claim 1, wherein the first semiconductor chip (RG2) includes a first multilayer wiring layer (M1-M4, Figure 3) , wherein the second semiconductor chip includes a second multilayer wiring layer (M1-M4, Figure 4) , wherein the first lower electrode is formed in the first multilayer wiring layer, wherein the first upper electrode is formed on the first multilayer wiring layer, wherein the second lower electrode is formed in the second multilayer wiring layer, wherein the second upper electrode is formed on the second multilayer wiring layer, wherein a thickness of the second multilayer wiring layer is smaller than a thickness of the first multilayer wiring layer (Figures 19-20 of Kaeriyama teaches lower and upper electrode for capacitor are formed at different level of wiring ) . Regarding claim 4, Figures 1- 4 of KUWAJIMA in view of Kaeriyama teach that the electronic device according to claim 1, wherein the first lower inductor and the first upper inductor are configured to be magnetically connectable to each other, and wherein the second lower inductor and the second upper inductor are configured to be magnetically connectable to each other ([0004] of KUWAJIMA) . Regarding claim 5, Figures 1- 4 of KUWAJIMA in view of Kaeriyama teach that the electronic device according to claim 1, wherein the first lower electrode and the first upper electrode are configured to be capacitively connectable to each other, and wherein the second lower electrode and the second upper electrode are configured to be capacitively connectable to each other ([0 095]-[0097] of Kaeriyama teaches capacitive coupling ) . Regarding claim 6, Figures 1- 4 of KUWAJIMA in view of Kaeriyama teach that the electronic device according to claim 1, comprising: a high-side unit (RG 2 is high voltage side, [0243])) ; and a low-side unit (RG1, [0243]) , wherein the high-side unit includes: a first circuit portion (RX1) applying the first potential to the first lower inductor; the first transformer; and a second circuit portion (TX2) applying the second potential to the first upper inductor, wherein the low-side unit includes: a third circuit portion (TX1) applying the third potential to the second lower inductor; the second transformer; and a fourth circuit portion (RX2) applying the fourth potential to the second upper inductor (Figure 1 of KUWAJIMA , [0069]-[0072] ) . Regarding claim 7, Figures 1- 4 of KUWAJIMA does not explicitly teach that the electronic device according to claim 6, wherein the first semiconductor device includes: the first semiconductor chip; and a high-side chip, wherein the first circuit portion and the first transformer are formed in the first semiconductor chip, wherein the second circuit portion is formed in the high-side chip, wherein the second semiconductor device includes: the second semiconductor chip; and a low-side chip, wherein the third circuit portion and the second transformer are formed in the second semiconductor chip, and wherein the fourth circuit portion is formed in the low-side chip. However, Figures 1-20 of Kaeriyama teaches alternating arrangement of inductor between a first chip and a second chip. Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device of KUWAJIMA in view of Kaeriyama as claimed in order to have flexible arrangement for different devices with a reasonable expectation of success since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). Regarding claim 8, Figures 1- 4 of KUWAJIMA does not explicitly teach that the electronic device according to claim 6, wherein the first semiconductor device includes: the first semiconductor chip; a first high-side chip; and a second high-side chip, wherein the first circuit portion is formed in the first high-side chip, wherein the second circuit portion is formed in the second high-side chip, wherein the first transformer is formed in the first semiconductor chip, wherein the second semiconductor device includes: the second semiconductor chip; a first low-side chip; and a second low-side chip, wherein the third circuit portion is formed in the first low-side chip, wherein the fourth circuit portion is formed in the second low-side chip, and wherein the second transformer is formed in the second semiconductor chip . However, Figures 1-20 of Kaeriyama teach alternating arrangement of inductor between a first chip and a second chip. Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device of KUWAJIMA in view of Kaeriyama as claimed in order to have flexible arrangement for different devices with a reasonable expectation of success since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). Regarding claim 9, Figures 1- 4 of KUWAJIMA in view of Kaeriyama teach that the electronic device according to claim 1, comprising: a high-side unit; and a low-side unit, wherein the high-side unit includes: a first circuit portion applying the first potential to the first lower electrode; the first capacitor; and a second circuit portion applying the second potential to the first upper electrode, wherein the low-side unit includes: a third circuit portion applying the third potential to the second lower electrode; the second capacitor; and a fourth circuit portion applying the fourth potential to the second upper electrode ( [0095]-[0097] of Kaeriyama teaches capacitive coupling ) . Regarding claim 10, Figures 1- 4 of KUWAJIMA in view of Kaeriyama teach that the electronic device according to claim 9, wherein the first semiconductor device includes: the first semiconductor chip; and a high-side chip, wherein the first circuit portion and the first capacitor are formed in the first semiconductor chip, wherein the second circuit portion is formed in the high-side chip, wherein the second semiconductor device includes: the second semiconductor chip; and a low-side chip, wherein the third circuit portion and the second capacitor are formed in the second semiconductor chip, and wherein the fourth circuit portion is formed in the low-side chip ([0095]-[0097] of Kaeriyama teaches capacitive coupling) . Regarding claim 11, Figures 1- 4 of KUWAJIMA does not teach that the electronic device according to claim 9, wherein the first semiconductor device includes: the first semiconductor chip; a first high-side chip; and a second high-side chip, wherein the first circuit portion is formed in the first high-side chip, wherein the second circuit portion is formed in the second high-side chip, wherein the first capacitor is formed in the first semiconductor chip, wherein the second semiconductor device includes: the second semiconductor chip; a first low-side chip; and a second low-side chip, wherein the third circuit portion is formed in the first low-side chip, wherein the fourth circuit portion is formed in the second low-side chip, and wherein the second capacitor is formed in the second semiconductor chip . However, Figures 1-20 of Kaeriyama teach alternating arrangement of coupling devices between a first chip and a second chip. Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device of KUWAJIMA in view of Kaeriyama as claimed in order to have flexible arrangement for different devices with a reasonable expectation of success since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). Regarding claim 12, Figures 1- 4 of KUWAJIMA in view of Kaeriyama do not teach that the electronic device according to claim 1, wherein the electronic device is configured to control an inverter. However, the above limitation does not distinguish the present invention over the prior art of KUWAJIMA in view of Kaeriyama who teaches the structure which is capable of performing the intended use as claimed. Moreover, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ 2d 1647 (1987). Regarding claim 13, Figures 1- 4 of KUWAJIMA in view of Kaeriyama teach that the electronic device according to claim 1, wherein the first lower inductor includes a first lower inductor wiring, wherein the first upper inductor includes a first upper inductor wiring, wherein the second lower inductor includes a second lower inductor wiring, wherein the second upper inductor includes a second upper inductor wiring, wherein a number of turns of the second lower inductor wiring is smaller than a number of turns of the first lower inductor wiring, and wherein a number of turns of the second upper inductor wiring is smaller than a number of turns of the first upper inductor wiring ( Figures 6-38 of KUWAJIMA and Figures 1-20 of Kaeriyama teach of using different size of inductors, and it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233. ) ([0160], Figures 1-38 of KUWAJIMA)([0122] of Kaeriyama). Regarding claim 14, Figures 1- 4 of KUWAJIMA in view of Kaeriyama teach that the electronic device according to claim 1, wherein the first lower inductor includes a first lower inductor wiring, wherein the first upper inductor includes a first upper inductor wiring, wherein the second lower inductor includes a second lower inductor wiring, wherein the second upper inductor includes a second upper inductor wiring, wherein a length of the second lower inductor wiring is smaller than a length of the first lower inductor wiring, and wherein a length of the second upper inductor wiring is smaller than a length of the first upper inductor wiring (Figures 6-38 of KUWAJIMA and Figures 1-20 of Kaeriyama teach of using different size of inductors, and it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233. ) ([0160], Figures 1-38 of KUWAJIMA)([0122] of Kaeriyama) . Regarding claim 15, Figures 1-38 of KUWAJIMA in view of Kaeriyama teach that the electronic device according to claim 1, wherein the first lower inductor includes a first lower inductor wiring, wherein the first upper inductor includes a first upper inductor wiring, wherein the second lower inductor includes a second lower inductor wiring, wherein the second upper inductor includes a second upper inductor wiring, wherein a cross-sectional area of the second lower inductor wiring in a cross section orthogonal to an extending direction of the second lower inductor wiring is smaller than a cross-sectional area of the first lower inductor wiring in a cross section orthogonal to an extending direction of the first lower inductor wiring, and wherein a cross-sectional area of the second upper inductor wiring in a cross section orthogonal to an extending direction of the second upper inductor wiring is smaller than a cross-sectional area of the first upper inductor wiring in a cross section orthogonal to an extending direction of the first upper inductor wiring (Figures 6-38 of KUWAJIMA and Figures 1-20 of Kaeriyama) . Regarding claim 16, Figures 1- 4 of KUWAJIMA do not explicitly teach that the electronic device according to claim 1, wherein an electrode area of the second lower electrode is smaller than an electrode are of the first lower electrode, and wherein an electrode area of the second upper electrode is smaller than an electrode are of the first upper electrode. However, KUWAJIMA teaches that the distance between the primary coil and the secondary coil determines the breakdown voltage in the transformer by having thickness of the insulating layer ([0199]), wherein by changing the distance and sizes provides different region to be operated differently with improved performance ([0206]). However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to improve the performance and reduce the size of the device and further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233. Examiner Notes A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT KHAJA AHMAD whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7991 . The examiner can normally be reached on FILLIN "Work schedule?" \* MERGEFORMAT Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHAJA AHMAD/ Primary Examiner, Art Unit 2813