DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 12, 14-15, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 12,396,192) in view of Ando et al. (US 2019/0326395) (“Ando”).
With regard to claim 1, fig. 33 of Hsu discloses a semiconductor device comprising: a substrate 401; an active pattern 402 extending in a first direction X on the substrate 401; a plurality of channel layers 4080 arranged on the active pattern 402 and spaced apart from each other in a vertical direction Z perpendicular to an upper surface (top of 401) of the substrate 401; a gate structure 450 crossing the active pattern 402, and surrounding the plurality of channel layers 4080, the gate structure 450 extending in a second direction Y that crosses the first direction X; and source/drain regions (440, 438) provided on the active pattern 402 on both sides of the gate structure 450, and comprising a first epitaxial layer 438 connected to each of side surfaces (left and right side of 4080 in fig. 33) of the plurality of channel layers 4080, and a second epitaxial layer 440 provided on the first epitaxial layer 438 and having a composition (“germanium content of the second epitaxial layer 440 is between about 32% and about 55%” col. 24 ll. 4-5) different from that of the first epitaxial layer (“first epitaxial layer 438 is between about 20% and 30%”, col 23 ll. 24-25), and wherein the first epitaxial layer 438 extends in the second direction Y and has a first thickness in the first direction X that is substantially constant.
Hsu does not disclose that each of the side surfaces of the plurality of channel layers has a crystal plane of (111) or (100).
However, fig. 2B of Ando discloses that each of the side surfaces (“exposed sidewalls surfaces of channel layers 413”, par [0036]) of the plurality of channel layers 413 has a crystal plane of (111) or (100) (“(100) crystal orientation”, par [0036]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the sidewall surfaces of the channel members of Hsu with the (100) crystal orientation as taught in Ando in order to permit rapid epitaxial growth. See par [0036] of Ando.
With regard to claim 2, fig. 33 of Hsu discloses that each of the first epitaxial layer 438 and the second epitaxial layer 440 comprises silicon germanium (SiGe) (“SiGe”, col. 23 ll. 10, col. 23 ll. 57-58), wherein the first epitaxial layer 438 has a first concentration of germanium (Ge) (“first epitaxial layer 438 is between about 20% and 30%”, col 23 ll. 24-25), the second epitaxial layer 440 has a second concentration of germanium (Ge) (“germanium content of the second epitaxial layer 440 is between about 32% and about 55%” col. 24 ll. 4-5) that is greater (55% > 20%) than the first concentration of germanium (Ge) (“first epitaxial layer 438 is between about 20% and 30%”, col 23 ll. 24-25).
With regard to claim 12, fig. 33 of Hsu discloses that the gate structure 450 comprises a gate electrode (“gate electrode layer”, col. 25 ll. 36) crossing the active pattern 402, surrounding the plurality of channel layers 4080, and extending along the second direction Y, and gate spacers 426 located on both side surfaces of the gate electrode (“gate electrode layer”, col. 25 ll. 36) extending along the second direction Y.
With regard to claim 14, fig. 33 of Hsu discloses internal spacer layers 426 provided on both side surfaces of the gate structure 450 under a lower surface of each of the plurality of channel layers 408 along the first direction X.
With regard to claim 15, fig. 33 of Hsu discloses a semiconductor device comprising: a substrate 401; a semiconductor channel 4080 on the substrate 401, the semiconductor channel 4080 having first (left side 4080, fig. 33) and second (right side 4080, fig. 33) side surfaces spaced apart from each other in a first direction X, and third (further side 4080, fig. 33) and fourth (closer side 4080, fig. 33) side surfaces spaced apart in a second direction Y that crosses the first direction X; first and second source/drain regions (438, 440) respectively provided on the first (left 4080) and second (right 4080) side surfaces of the semiconductor channel 4080; and a gate structure 450 surrounding an upper surface (top of 4080) and the third (further side 4080and fourth side surfaces of the semiconductor channel 4080 and extending in the second direction Y, wherein each of the first and second source/drain regions (438, 440) comprises a first epitaxial layer 438 provided on the first (left side 4080, fig. 33) and second (right side 4080, fig. 33) side surfaces of the semiconductor channel 4080 and a second epitaxial layer 440 provided on the first epitaxial layer 438 and having a composition (“germanium content of the second epitaxial layer 440 is between about 32% and about 55%” col. 24 ll. 4-5) different from that of the first epitaxial layer (“first epitaxial layer 438 is between about 20% and 30%”, col 23 ll. 24-25), the first epitaxial layer 438 extends in the second direction Y and has a first thickness in the first direction X that is substantially constant, and wherein a cross section of each of the first and second source/drain regions (438, 440) along the second direction Y has a rectangular shape.
With regard to claim 17, fig. 33 of Hsu discloses that the semiconductor channel 408 comprises an active pattern 401 that protrudes from the upper surface of the substrate 401 and extends in the first direction X, and a plurality of channel layers 4080 stacked on the active pattern 402 and spaced apart from each other in a direction perpendicular Z to the upper surface of the substrate 401.
With regard to claim 20, fig. 33 of Hsu discloses that the cross section of each of the first and second source/drain regions (438, 440, 442) has the rectangular shape in which both upper corners are chamfered to form a chamfered surface (upper corner 442 are sloped).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 12,396,192), Ando et al. (US 2019/0326395) (“Ando”), and Yang et al. (US 2019/0067490) (“Yang”).
With regard to claim 4, Hsu and Ando do not disclose comprises a middle epitaxial layer that comprises silicon germanium and is provided between the first epitaxial layer and the second epitaxial layer, and wherein a third concentration of germanium (Ge) in the middle epitaxial layer is higher than the first concentration and lower than the second concentration.
However, fig. 2 of Yang discloses a middle epitaxial layer 107c that comprises silicon germanium (“first to third epitaxial layers 107b to 107d may include SiGe”, par [0032]) and is provided between the first epitaxial layer 107b and the second epitaxial layer 107d, and wherein a third concentration (“second epitaxial layer 107c may include 37 at %”, par [0033]) of germanium (Ge) in the middle epitaxial layer 107c is higher than the first concentration (“ first epitaxial layer 107b may include 17 at %”, par [0033]) and lower than the second concentration (“third epitaxial layer 107d may include 50 at %”, par [0033]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the source/drain regions of Hsu with the three epitaxial layers as taught in Yang in order to provide a semiconductor device having improved alternating current (AC) characteristics by reducing enlargement of the gate length thereof. See par [0079] of Yang.
With regard to claim 5, Hsu and Ando do not disclose that the middle epitaxial layer extends in the second direction on a side surface of an uppermost channel layer, among the plurality of channel layers, and has a second thickness in the first direction that is substantially constant.
However, fig. 2 of Yang discloses that the middle epitaxial layer 107c extends in the second direction Y on a side surface of an uppermost channel layer (top 120), among the plurality of channel layers 120, and has a second thickness in the first direction X that is substantially constant.
Therefore, it would have been obvious to one of ordinary skill in the art to form the source/drain regions of Hsu with the three epitaxial layers as taught in Yang in order to provide a semiconductor device having improved alternating current (AC) characteristics by reducing enlargement of the gate length thereof. See par [0079] of Yang.
Claims 9-10 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 12,396,192), Ando et al. (US 2019/0326395) (“Ando”), and Ching et al. (US 2020/0043810) (“Ching”).
With regard to claim 9, Hsu and Ando do not disclose that the upper surface of the substrate is a (100) crystal plane rotated by 45 degrees with respect to an axis perpendicular to the upper surface.
However, Ching discloses that the upper surface of the substrate is a (100) crystal plane rotated by 45 degree (“(100) rotated 45-degree”, par [0042]) with respect to an axis perpendicular to the upper surface (“top surface crystal orientation”, par [0042]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the substrate of Hsu with the crystal orientation as taught in Ching in order to optimize the electron or hole transport of the channels. See par [0042] of Ching.
With regard to claim 10, fig. 33 of Hsu discloses a cross section of a source/drain region (440, 438), among the source/drain regions, in the second direction Y has a rectangular shape with an upper side (top of 440, 438) that is parallel to the upper surface of the substrate 401.
With regard to claim 22, Hsu and Ando do not disclose that the upper surface of the substrate is a (100) crystal plane rotated by 45 degrees with respect to an axis perpendicular to the upper surface.
However, Ching discloses that the upper surface of the substrate is a (100) crystal plane rotated by 45 degree (“(100) rotated 45-degree”, par [0042]) with respect to an axis perpendicular to the upper surface (“top surface crystal orientation”, par [0042]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the substrate of Hsu with the crystal orientation as taught in Ching in order to optimize the electron or hole transport of the channels. See par [0042] of Ching.
Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 12,396,192), Ando et al. (US 2019/0326395) (“Ando”), Ching et al. (US 2020/0043810) (“Ching”), and Adam et al. (US 2014/0027863) (“Adam”).
With regard to claim 11, Hsu, Ando, and Ching do not disclose in the cross section in the second direction, a top surface of the source/drain region is a (100) crystal plane, and a side surface of the source/drain region is a (100) crystal plane.
However, Adam discloses in the cross section in the second direction, a top surface of the source/drain region is a (100) crystal plane (“top surfaces and sidewalls of the two or more fins are (100) surfaces”, par [0003]), and a side surface of the source/drain region is a (100) crystal plane (“top surfaces and sidewalls of the two or more fins are (100) surfaces”, par [0003]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the source/drain of Hsu with the top and sidewalls as taught in Adam in order to grow epitaxial semiconductor material on the exposed ends. See par [0003] of Adam.
With regard to claim 18, Hsu, Ando, and Ching do not disclose in the cross section along the second direction, each of the first and second source/drain regions has a top surface that is a (100) crystal plane and a side surface that is a (100) crystal plane.
However, Adam discloses in the cross section along the second direction, each of the first and second source/drain regions has a top surface that is a (100) crystal plane (“top surfaces and sidewalls of the two or more fins are (100) surfaces”, par [0003]) and a side surface that is a (100) crystal plane (“top surfaces and sidewalls of the two or more fins are (100) surfaces”, par [0003]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the source/drain of Hsu with the top and sidewalls as taught in Adam in order to grow epitaxial semiconductor material on the exposed ends. See par [0003] of Adam.
Allowable Subject Matter
Claims 6-8, 13, 19, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 23 is allowed.
In claim 23, closest prior art figs. 2B-2F of Ando et al. (US 2019/0326395) (“And”) discloses a semiconductor device comprising: a substrate 101 having an upper surface that is a (110) crystal plane (“(110)”, par [0026]); a semiconductor channel 413 on the substrate 101, the semiconductor channel 413 having first (left side 413, fig. 2B) and second side surfaces (right side 413, fig. 2B) spaced apart from each other in a first direction (left to right, fig. 2B), and third (further side 413, fig. 2B) and fourth side (closer side 413, fig. 2B) surfaces spaced apart in a second direction (in and out of page in fig. 2B) that crosses the first direction (left to right in fig. 2B); first and second source/drain regions 101 respectively provided on the first and second side surfaces (left and right side of 413 in fig. 2B) of the semiconductor channel 413, each of the first side and the second side of the semiconductor channel having a (111) crystal plane; and a gate structure 210 surrounding an upper surface (top of 413) and the third and fourth side surfaces (further and closer sides of 413) of the semiconductor channel 413, and extending in the second direction (in and out of page in fig. 2E), the second direction of the substrate corresponding to a <112> crystal direction.
Conclusion
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
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