DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-7) in the reply filed on 4/20/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 3, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Briggs et al. (2018/0040510, hereafter Briggs) in view of Kim et al. (2004/0173831, hereafter Kim).
Regarding claim 1, Briggs discloses a semiconductor device, comprising: a first substrate (1202, Fig. 14, par.0065); a transistor (par. 0037) disposed on the first substrate; and a first interconnection layer connected to the transistor (1002, Fig. 10, par. 0061), wherein the first interconnection layer comprises a first conductive line (1101A, Fig. 14, par. 0064), a second conductive line (1401B, Fig. 14, par. 0068), and a third conductive line (1101B, Fig. 14, par. 0064), which are spaced apart from each other in a first direction parallel to a top surface of the first substrate (Fig. 1, par. 0046), wherein the second conductive line is disposed between the first conductive line and the third conductive line, and wherein a top surface of the second conductive line is located at a height higher than top surfaces of the first and third conductive lines with respect to the top surface of the first substrate (Fig. 14).
Briggs fails to disclose wherein the first interconnection layer further comprises a first pattern insulating layer interposed between the first and second conductive lines and between the second and third conductive lines, and wherein the first pattern insulating layer extends along a bottom surface of the second conductive line and extends to regions on the top surfaces of the first and third conductive lines.
However, Kim teaches wherein the first interconnection layer (150) further comprises a first pattern insulating layer (153) interposed between the first (151 left) and second (155) conductive lines and between the second and third (151 right) conductive lines, and wherein the first pattern insulating layer extends along a bottom surface of the second conductive line and extends to regions on the top surfaces of the first and third conductive lines (Fig. 1B).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Briggs with Kim by providing an insulating pattern between conductive lines such that it goes under the middle and over the adjacent lines in order to electrically isolate adjacent interconnects while providing structural support.
Regarding claim 3, Briggs discloses a semiconductor device wherein the top surfaces of the first (1101A) and third (1101B) conductive lines are located at a same level (Fig. 14, par. 0064).
Regarding claim 7, Briggs discloses a semiconductor device wherein the first to third conductive lines comprise tungsten (W) (par. 0048).
Claim 2, 4, 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Briggs in view of Kim as applied to claim 1 above, and further in view of Yang et al. (2021/0217760, hereafter Yang).
Regarding claim 2, Briggs discloses the second interconnection layer comprising a fourth conductive line (1101A, par. 0064), a fifth conductive line (1401B, par. 0068), and a sixth conductive line (1101B, par. 0064), which are spaced apart from each other in the first direction, the fifth conductive line is disposed between the fourth conductive line and the sixth conductive line; and a top surface of the fifth conductive line is located at a height higher than top surfaces of the fourth and sixth conductive lines with respect to the top surface of the first substrate (Fig. 14).
Briggs fails to disclose a semiconductor device further comprising a second interconnection layer disposed on the first interconnection layer.
However, Yang teaches a semiconductor device further comprising a second interconnection layer (ST3, Fig. 3A, par. 0108) disposed on the first interconnection layer (ST1, Fig. 3A, par. 0086).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Briggs with Yang by providing multiple interconnection layers on each other in order to minimize signal delay.
Regarding claim 4, Briggs discloses a semiconductor device wherein the top surfaces of the fourth (1101A, par. 0064) and sixth (1101B, par. 0064) conductive lines are located at a same level (Fig. 14).
Regarding claim 5, Briggs fails to disclose a semiconductor device further comprising: a contact connected to a terminal of the transistor, wherein the second conductive line penetrates the first pattern insulating layer to be electrically connected to the contact.
However, Yang teaches a semiconductor device further comprising: a contact (ETHV1, par. 0094) connected to a terminal (50a, par. 0107) of the transistor, wherein the second conductive line (VPb middle, Fig. 3A, 0105) penetrates the first pattern insulating layer (3, Fig. 3A, 0104) to be electrically connected to the contact (Fig. 3A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Briggs with Yang by having a connection to contact by penetrating the insulation in order to minimize parasitic capacitance and provide a path or signal routing.
Regarding claim 6, Briggs fails to disclose a semiconductor device further comprising: a contact connected to one of the conductive lines of the first interconnection layer; and a second pattern insulating layer interposed between the fourth and fifth conductive lines and between the fifth and sixth conductive lines, wherein the second pattern insulating layer extends along a bottom surface of the fifth conductive line, wherein the fifth conductive line penetrates the second pattern insulating layer to be electrically connected to the contact.
However, Yang teaches a semiconductor device further comprising: a contact (CTHV3, par. 0114) connected to one of the conductive lines (VPb) of the first interconnection layer (ST1, par. 0086); and a second pattern insulating layer (3) interposed between the fourth and fifth conductive lines and between the fifth and sixth conductive lines (VPb top), wherein the second pattern insulating layer extends along a bottom surface of the fifth conductive line, wherein the fifth conductive line penetrates the second pattern insulating layer to be electrically connected to the contact (Fig. 3A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Briggs with Yang by insulating the fifth conductive line from the fourth and sixth and having a connection to a contact by penetrating the insulation in order to minimize parasitic capacitance and provide a path or signal routing.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.M.B./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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