DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 25-27 and 29-39 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 25-27, and 29-39 use the acronym “MRS”. Although claim 22 defines the acronym “MRS”, claims 25, 26, and 29-39 are not dependent on claim 22.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21, 24, 29, 30, and 40 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Huang et al. US 2019/0311290 A1 (“Huang”).
As to claim 21, Huang discloses a device for verifying a circuit design comprising a first circuit block and a second circuit block, the device comprising:
a vector generator configured to determine a first verification vector based on a first test vector (Paragraphs 5-6 or 42-43 -e.g., machine learning models for test pattern generation) corresponding to characteristics of state transition of the first circuit block and first reinforcement learning (Paragraphs 32-35 or 43 — e.g., analysis of circuit values or transitions via scan chains or outputs, reinforcement learning necessary in a trained machine learning model), and a second verification vector based on a second test vector (Paragraphs 5-6 or 42-43 -e.g., machine learning models for test pattern generation) corresponding to characteristics of state transition of the second circuit block and second reinforcement learning (Paragraphs 32-35 or 43 — e.g., analysis of circuit values or transitions via scan chains or outputs, reinforcement learning necessary in a trained machine learning model); and
a design verifier configured to perform a first design verification on the first circuit block by using the first verification vector, and a second design verification on the second circuit block by using the second verification vector (Paragraphs 4-6 or 32-33 - e.g., the goal of configuration/generation is to determine actual testing used to verify the devices).
As to claim 24, Huang discloses the device of claim 21. Huang further discloses wherein the vector generator generates a positive or negative reward depending on whether new state transition occurs in the first circuit block by the first test vector, and applies the generated positive or negative reward to the first reinforcement learning (Paragraphs 5-6 or 42-43 -e.g., necessary in training machine learning models for test pattern generation using test data).
Claims 29 and 40 recite elements similar to claim 21, and are rejected for the same reasons. The examiner notes that Huang discloses circuit elements such as scan cells or shift registers (e.g., Huang Paragraphs 33 or 40) which are testability features, and would be handled/classified differently during verification.
As to claim 30, Huang discloses the device of claim 29. Huang further discloses wherein the verification characteristics comprise characteristics of parameters that generate state transition of the circuit block (Paragraphs 32-35 or 43 — e.g., analysis of circuit values or transitions via scan chains or outputs).
Allowable Subject Matter
Claims 22, 23, and 28 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 25-27 and 31-39 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest a device or system for verifying a circuit design having the combination of elements of the claims including, among other elements, the circuit and learning details of the claims used in the vector generation and design verification elements of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYCE M AISAKA whose telephone number is (571)270-5808. The examiner can normally be reached M-F: 6:30AM-5:00PM PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571)272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYCE M AISAKA/ Primary Examiner, Art Unit 2851
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