DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/16/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 3/20/2026 is acknowledged.
Claims 7-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/20/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ikeda (US 2020/0388618 A1).
Regarding independent claim 1, Figures 2K-3K of Ikeda disclose a semiconductor structure, comprising:
a substrate S (“substrate”- ¶0013), wherein a plurality of capacitor contact structures CC (“capacitor contacts”- ¶0013) arranged at intervals are formed on the substrate S;
an isolation structure IS (“isolation structure”- ¶0015), wherein the isolation structure IS is disposed on the substrate S and between adjacent capacitor contact structures CC, and a top surface of the isolation structure IS is not higher than a top surface of each capacitor contact structure CC; and
an isolation groove (i.e., the openings in isolation structure IS formed at and shown in Figs. 2D-3D -¶0023, which later become filled grooves), wherein the isolation groove extends from the top surface of the isolation structure IS to an interior of the isolation structure IS, and a spacing is provided between the isolation groove and the capacitor contact structure CC.
Regarding claim 2, Figures 2K-3K of Ikeda disclose wherein the plurality of capacitor contact structures CC are arrayed in a plurality of rows and a plurality of columns, the plurality of the capacitor contact structures CC of a same column are arranged at intervals in a first direction, the plurality of the capacitor contact structures CC of a same row are arranged at intervals in a second direction, and the second direction intersects the first direction; and
the isolation groove comprises a plurality of first isolation grooves (i.e., the openings in IS2 formed at and shown in Figs. 2D-3D -¶0023, which later become filled grooves), arranged at intervals, and the first isolation grooves extend in the first direction and are disposed between two adjacent columns of the capacitor contact structures CC (see Figs. 2D-3D for better clarification- ¶0023).
Regarding claim 4, Figures 2K-3K of Ikeda disclose the semiconductor structure further comprising a plurality of capacitor structures SC (“capacitor”- ¶0014), wherein the capacitor structures SC are disposed on the substrate SS, and are in contact with the capacitor contact structures CC in a one-to-one correspondence.
Regarding independent claim 20, Figures 2K-3K of Ikeda disclose a dynamic random access memory (¶0001) comprising a semiconductor structure, wherein the semiconductor structure comprises:
a substrate S (“substrate”- ¶0013), wherein a plurality of capacitor contact structures CC (“capacitor contacts”- ¶0013) arranged at intervals are formed on the substrate S;
an isolation structure IS (“isolation structure”- ¶0015), wherein the isolation structure IS is disposed on the substrate S and between adjacent capacitor contact structures CC, and a top surface of the isolation structure IS is not higher than a top surface of each capacitor contact structure CC; and
an isolation groove (i.e., the openings in isolation structure IS formed at and shown in Figs. 2D-3D -¶0023, which later become filled grooves), wherein the isolation groove extends from the top surface of the isolation structure IS to an interior of the isolation structure IS, and a spacing is provided between the isolation groove and the capacitor contact structure CC.
Allowable Subject Matter
Claims 3 and 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art of record including Ikeda, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the isolation groove comprises a plurality of second isolation grooves, arranged at intervals, the second isolation grooves extend in the second direction, are disposed between two adjacent rows of the capacitor contact structures, and penetrate through a plurality of the first isolation grooves”.
Regarding claim 5 (which claim 6 depends from), the prior art of record including Ikeda, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the] semiconductor structure… further comprising a support structure, wherein the support structure comprises a first support layer, a second support layer, and a third support layer that are sequentially stacked from bottom to top, and the support structure comprises a plurality of capacitor holes penetrating the first support layer, the second support layer, and the third support layer, wherein the capacitor holes are arranged in a one-to-one correspondence with the capacitor contact structures, and the capacitor holes expose the capacitor contact structures; wherein the isolation groove penetrates the first support layer in a thickness direction; and wherein the capacitor structure comprises: a lower electrode, wherein the lower electrode is disposed on a sidewall and a bottom of the capacitor hole, is connected to each of the first support layer, the second support layer, and the third support layer, and is in contact with the capacitor contact structure; a capacitor dielectric layer, wherein the capacitor dielectric layer is disposed on a surface of the lower electrode and in the isolation groove; and an upper electrode, wherein the upper electrode is disposed on a surface of the capacitor dielectric layer”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Jhan et al. (US 2022/0139922 A1), which discloses a semiconductor structure comprising capacitor contact structures surrounded by an isolation structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C CHANG/Primary Examiner, Art Unit 2817
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