DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 05/11/2026. Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 12/30/2023.
Oath/Declaration
The oath or declaration filed on 11/16/2023 is acceptable.
Election/Restrictions
Applicant’s election, with traverse, of invention I, Species I: claims 1-8 and 20, in the “Response to Election / Restriction Filed” filed on 05/11/2026 is acknowledged. The traversal is on the ground(s) that, restriction requirement. Under MPEP § 806.05(f), restriction between a product and a process of making that product is proper where (1) the process as claimed can be used to make another materially different product, or (2) the product as claimed can be made by another materially different process. Applicant respectfully submits that the Restriction Requirement has not sufficiently established either circumstance. The method of claim 9 recites forming the same semiconductor structure with the same structural relationships recited in claim 1.
Examiner like to note that method claim 9 recites “forming a plurality of word line structures in the substrate” is not required for the device claim 1, such as “a substrate, comprising an array region and a peripheral region; and a word line structure, comprising a first conductive layer disposed on the substrate”, which required different process steps.
In addition, Applicant further notes that the Restriction Requirement contains internal inconsistencies regarding the species requirement, including whether the species requirement applies upon election of Invention II and whether Species M.III corresponds to Figs. 14-23 or Figs. 14-24. These inconsistencies further indicate that the species requirement is unclear and improper.
Upon election, i.e., the Inventions I or II, applicant is further required under 35 U.S.C. 121 to elect a single one of the following disclosed species to which prosecution shall be restricted should no generic claim be finally held allowable:
A semiconductor device, as described in (Figs.2-3).
A semiconductor device, as described in (Figs.4-13).
A semiconductor device, as described in (Figs. 14-23).
The species of different device, Species M. I-M.III, as claimed are independent or distinct because they have been disclosed as separate embodiments and Figures, and are characterized by mutually exclusive characteristics, regarding Species M. I- M.III, mutually exclusive features of “The word line structure 2 may include a first conductive layer 21 disposed on (and within the boundary of) the substrate 1. The first conductive layer 21 penetrates the array region 101 and extends to the peripheral region 102 in a first direction A. In a normal direction of the substrate 1, a height of the first conductive layer 21 on a surface of the peripheral region 102 is higher than a height of the first conductive layer 21 on a surface of the array region 102. ", as describe in (Figure [2-3]), for Species M.I, and features of “the word line contact plug 6 may penetrate the insulating layer 5 in a normal direction of the substrate 1, that is, the word line contact plug 6 may be embedded into the insulating layer 5. The insulating layer 5 may protect the word line contact plug 6. In such a process, coupling or a short circuit between the word line contact plug 6 and another surrounding structure may be avoided, thereby further improving a product yield.”, as describe in (Figure [4-13]), for Species M.II, and features of “a first contact hole 601 may be formed in the peripheral region 102 by using an etching process, and the first contact hole 601 may expose a word line structure 2. In some embodiments, the first contact hole 601 may alternatively be formed in another method. A method for forming the first contact hole 601 is not specifically limited herein.”, as describe in (Figure [14-24], Para [0096]), for Species M.III.
The requirement is still deemed proper and is therefore made FINAL.
This office action considers claims 1-20 are thus pending for prosecution, of which, claims 9-19 are withdrawn, and claims 1-8 and 20 examined on their merits.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “a word line contact plug, disposed in the peripheral region, wherein a bottom surface of the word line contact plug is connected to the first conductive layer”, claim 2, lines 2-3 and “a second conductive layer, wherein the second conductive layer is disposed on the first conductive layer, and an orthographic projection of the second conductive layer on the substrate does not overlap an orthographic projection of the word line contact plug on the substrate.” Claim 3, lines 2-4, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Claim 1, The instant claims recite limitation “a normal direction of the substrate, a height of the first conductive layer on a surface of the peripheral region is higher than a height of the first conductive layer on a surface of the array region” is not clear because a normal direction is not defined. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 2, The instant claims recite limitation “a word line contact plug, disposed in the peripheral region, wherein a bottom surface of the word line contact plug is connected to the first conductive layer” is not clear because a bottom surface of the word line contact plug appears not connected to the first conductive layer. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 20, The instant claims recite limitation “a normal direction of the substrate, a height of the first conductive layer on a surface of the peripheral region is higher than a height of the first conductive layer on a surface of the array region” is not clear because a normal direction is not defined. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claims 2-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, because of their dependency status from claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 2013/0056823 A1; hereafter Kim).
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Regarding claim 1. Kim discloses a semiconductor structure, comprising:
a substrate (Fig 12, substrate 100, Para [ 0095]), comprising an array region (Fig 12, cell region) and a peripheral region (Fig 12, peripheral region); and
a word line structure ([barrier layer 130, a metal layer 132 and a capping layer 134], construed as word line structure, Para [ 0095]), comprising a first conductive layer (barrier layer 130, Para [ 0095]) disposed on the substrate (Fig 12, substrate 100, Para [ 0095]), wherein the first conductive layer (barrier layer 130, Para [ 0095]) penetrates the array region (barrier layer 130, Para [ 0095]) and extends to the peripheral region in a first direction (Fig 12, barrier layer 130, Para [ 0095]);
in a normal direction of the substrate (Fig 12, substrate 100, Para [ 0095]), a height of the first conductive layer (Fig 12, barrier layer 130, Para [ 0095]) on a surface of the peripheral region (Fig 12, peripheral region) is higher than a height of the first conductive layer (Fig 12, barrier layer 130, Para [ 0095]) on a surface of the array region (Fig 12, cell region).
Regarding claim 20. Kim discloses a memory, comprising a semiconductor structure, wherein the semiconductor structure comprises:
a substrate (Fig 12, substrate 100, Para [ 0095]), comprising an array region (Fig 12, cell region) and a peripheral region (Fig 12, peripheral region); and a word line structure ([barrier layer 130, a metal layer 132 and a capping layer 134], construed as word line structure, Para [ 0095]), comprising a first conductive layer (barrier layer 130, Para [ 0095]) disposed on the substrate (Fig 12, substrate 100, Para [ 0095]), wherein the first conductive layer (barrier layer 130, Para [ 0095]) penetrates the array region (barrier layer 130, Para [ 0095]) and extends to the peripheral region (Fig 12, peripheral region) in a first direction (barrier layer 130, Para [ 0095]);
in a normal direction of the substrate (Fig 12, substrate 100, Para [ 0095]), a height of the first conductive layer (Fig 12, barrier layer 130, Para [ 0095]) on a surface of the peripheral region (Fig 12, peripheral region) is higher than a height of the first conductive layer (Fig 12, barrier layer 130, Para [ 0095]) on a surface of the array region (Fig 12, cell region).
Alternate Rejection:
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 2008/0067692 A1; hereafter Kim).
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Regarding claim 1. Kim discloses a semiconductor structure, comprising:
a substrate (Fig 3, substrate 100, Para [ 0069]), comprising an array region (Fig 3, active area A, Para [ 0070]) and a peripheral region (Fig 3, peripheral circuit area B, Para [ 0070]); and
a word line structure ([conductive layer 154a/154b, capping layers 156a/156b], construed as word line structure, Para [ 0085]), comprising a first conductive layer (conductive layer 154a/154b, Para [ 0085]) disposed on the substrate (Fig 12, substrate 100, Para [ 0069]), wherein the first conductive layer (conductive layer 154a/154b, Para [ 0085]) penetrates the array region (Fig 3, active area A, Para [ 0070]) and extends to the peripheral region (Fig 12, peripheral circuit area B, Para [ 0070]) in a first direction;
in a normal direction of the substrate (Fig 3, substrate 100, Para [ 0069]), a height of the first conductive layer (conductive layer 154a/154b, Para [ 0085]) on a surface of the peripheral region (Fig 3, peripheral circuit area B, Para [ 0070]) is higher than a height of the first conductive layer (conductive layer 154a/154b, Para [ 0085]) on a surface of the array region (Fig 3, active area A, Para [ 0070]).
Regarding claim 2. Kim discloses the semiconductor structure according to claim 1, Kim further discloses wherein the semiconductor structure further comprises:
a word line contact plug (metal barrier layer 152b), disposed in the peripheral region (Fig 3, peripheral circuit area B, Para [ 0070]), wherein a bottom surface of the word line contact plug (Fig 3, peripheral circuit area B, Para [ 0070]) is connected to the first conductive layer (conductive layer 154a/154b, Para [ 0085]).
Regarding claim 20. Kim discloses a memory, comprising a semiconductor structure, wherein the semiconductor structure comprises:
a substrate (Fig 3, substrate 100, Para [ 0069]), comprising an array region (Fig 3, active area A, Para [ 0070]) and a peripheral region (Fig 3, peripheral circuit area B, Para [ 0070]); and
a word line structure ([conductive layer 154a/154b, capping layers 156a/156b], construed as word line structure, Para [ 0085]), comprising a first conductive layer (conductive layer 154a/154b, Para [ 0085]) disposed on the substrate (Fig 12, substrate 100, Para [ 0069]), wherein the first conductive layer (conductive layer 154a/154b, Para [ 0085]) penetrates the array region (Fig 3, active area A, Para [ 0070]) and extends to the peripheral region (Fig 12, peripheral circuit area B, Para [ 0070]) in a first direction;
in a normal direction of the substrate (Fig 3, substrate 100, Para [ 0069]), a height of the first conductive layer (conductive layer 154a/154b, Para [ 0085]) on a surface of the peripheral region (Fig 3, peripheral circuit area B, Para [ 0070]) is higher than a height of the first conductive layer (conductive layer 154a/154b, Para [ 0085]) on a surface of the array region (Fig 3, active area A, Para [ 0070]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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