DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1 and 20.
Pending: 1-20.
Withdrawn: 12.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 11/17/2023 and 9/6/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Election/Restrictions
Applicant’s election without traverse of Species I (fig. 10 and 13) claim 1-11 and 13-20 in the reply filed on 2/6/2026 is acknowledged.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DISPLAY DEVICE WITH DEMULTIPLEXER SWITCH CIRCUITS AND INTERVENING SHIELD LINES.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10, 14-15 and 20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Cho et al., US PG pub. 20200357345 A1 (Cho’345); in view of Cho et al., US PG pub. 20210273035 A1 (Cho’035).
Re: Independent Claim 1, Cho ‘345 discloses a substrate (101, fig. 5; ¶0094) including a main area (MR, fig. 4) and a sub-area (SR, fig. 4) protruding from one side of the main area (MR, fig. 4) in a first direction (DR1, fig. 4), the main area (MR, fig. 4) including a display area (DA, fig. 4) in which pixels are (PX as shown in figure 4) arranged and a non-display area (NDA, fig. 4) surrounding the display area (DA, fig. 4), and the sub-area (SR, fig. 4) including a demultiplexer area (area 60, fig. 4) and a bending area (BR, fig. 4) positioned between the demultiplexer area (area 60, fig. 5) and the main area (MR, fig. 4); and
a circuit layer (Circuit as shown in figure 6) disposed on the substrate (101; ¶0094) and including pixel circuits (PX circuit, fig. 3) of the pixels arranged in the display area (DA, fig. 4) at a first pitch in a second direction (DR2, fig. 4) crossing the first direction (DR1, fig. 4), data lines (DL, fig. 15) connected to the pixel circuits (PX circuit, fig. 3), and demultiplexer circuits (DEMUX, fig. 2) arranged in the demultiplexer area (area 60, fig. 4) at the first pitch in the second direction (DR2, fig. 4) and including first switches (T.sub.DM1, fig. 2) and second switches (T.sub.DM2, fig. 2), wherein the circuit layer (Circuit as shown in figure 6) further includes: first lines (DL(2i-1), fig. 2) connected to the first switches (T.sub.DM1, fig. 2), respectively, and second lines (DL(2i), fig. 2) connected to the second switches (T.sub.DM2, fig. 2), respectively, the first lines (DL(2i-1), fig. 2) and the second lines (DL(2i), fig. 2) extending from the demultiplexer area (area 60, fig. 4) to the main area (MR, fig. 4) through the bending area (BR, fig. 4) and connecting the first switches (T.sub.DM1, fig. 2) and the second switches (T.sub.DM2, fig. 2) to the data lines (DL, fig. 15), respectively.
Cho’345 is silent regarding: shield lines disposed between adjacent first lines (DL(2i-1), fig. 2) and the second lines (DL(2i), fig. 2), respectively.
Cho‘035 discloses a shield lines (SH, fig. 15) disposed between adjacent first lines (DL_E, fig. 15) and the second lines (DL_0, fig. 15), respectively.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a shield lines between two data line since this can prevent occurrence of a coupling capacitor which could cause component failure or signal distortion.
Re: Claim 2, Cho’345 discloses all the limitations of claim 1 on which this claim depends. Cho’345 further discloses: wherein the first lines (DL(2i-1), fig. 2) and the second lines (DL(2i), fig. 2) are formed as straight lines (DL in a straight lines as shown in figure 15) extending in the first direction (DR1, fig. 4) in the demultiplexer area (area 60, fig. 4), the bending area (BR, fig. 4), and the main area (MR, fig. 4).
Re: Claim 3, Cho’345 discloses all the limitations of claim 1 on which this claim depends. Cho’345 further discloses: wherein the sub-area (SR, fig. 4) further includes a first line (DL(2i-1 as shown in figure 15) crossing area positioned between the demultiplexer area (area 60, fig. 4) and the bending area (BR, fig. 4), and a first second line (DL(2i as shown in figure 15) crossing area positioned between the bending area (BR, fig. 4) and the main area (MR, fig. 4).
Re: Claim 4, Cho’345 discloses all the limitations of claim 3 on which this claim depends. Cho’345 further discloses: wherein, in the demultiplexer area (area 60, fig. 4) and the main area (MR, fig. 4), the first lines (DL(2i-1), fig. 2) and the second lines (DL(2i), fig. 2) are arranged along the second direction (DR2, fig. 4) in a first order, and
wherein, in the bending area (BR, fig. 4), the first lines (DL(2i-1), fig. 2) and the second lines (DL(2i), fig. 2) are arranged along the second direction (DR2, fig. 4) in a second order different from the first order.
Cho’345 is silent regarding: wherein the shield lines are disposed between adjacent first line (DL(2i-1 as shown in figure 15) groups each including at least two first lines (DL(2i-1), fig. 2) and first second line (DL(2i as shown in figure 15) groups each including at least two second lines (DL(2i), fig. 2), respectively.
Cho‘035 discloses a shield lines (SH, fig. 15) disposed between adjacent first lines (DL_E, fig. 15) and the second lines (DL_0, fig. 15), respectively.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a shield lines between two data line since this can prevent occurrence of a coupling capacitor which could cause component failure or signal distortion.
Re: Claim 5, Cho’345 discloses all the limitations of claim 4 on which this claim depends. Cho’345 further discloses: wherein, in the first line (DL(2i-1 as shown in figure 15) crossing area, some of the first lines (DL(2i-1), fig. 2) and some of the second lines (DL(2i), fig. 2) cross each other, and
wherein, in the first second line (DL(2i as shown in figure 15) crossing area, the some of the first lines (DL(2i-1), fig. 2) and the some of the second lines (DL(2i), fig. 2) cross each other such that an arrangement order of the first lines (DL(2i-1), fig. 2) and the second lines (DL(2i), fig. 2) is the same as an arrangement order of the first lines (DL(2i-1), fig. 2) and the second lines (DL(2i), fig. 2) in the demultiplexer area (area 60, fig. 4).
Re: Claim 6, Cho’345 discloses all the limitations of claim 1 on which this claim depends. Cho’345 is silent regarding: wherein the first lines (DL(2i-1), fig. 2), the second lines (DL(2i), fig. 2), and the shield lines are arranged at uniform intervals along the second direction (DR2, fig. 4) in the bending area (BR, fig. 4).
Cho‘035 discloses a shield lines (SH, fig. 15; shield line SH is in each pixel would have been form uniform intervals) disposed between adjacent first lines (DL_E, fig. 15) and the second lines (DL_0, fig. 15).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a shield lines between two data line since this can prevent occurrence of a coupling capacitor which could cause component failure or signal distortion.
Re: Claim 7, Cho’345 discloses all the limitations of claim 1 on which this claim depends. Cho’345 further discloses: wherein the first switches (T.sub.DM1, fig. 2) are turned on by a first clock signal (CL1, fig. 2) and the second switches (T.sub.DM2, fig. 2) are turned on by a second clock signal (CL2, fig. 2).
Re: Claim 8, Cho’345 discloses all the limitations of claim 1 on which this claim depends. Cho’345 further discloses: wherein the circuit layer (Circuit as shown in figure 6) further includes a power line (¶0067) positioned in the main area (MR, fig. 4) and the sub-area (SR, fig. 4), and connected to the pixels.
Cho’345 is silent regarding: wherein the shield lines are connected to the power line around the bending area (BR, fig. 4).
Cho‘035 discloses a shield lines (SH, fig. 15) are connected to power lines (¶0018).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a shield lines between two data line since this can prevent occurrence of a coupling capacitor which could cause component failure or signal distortion.
Re: Claim 9, Cho’345 discloses all the limitations of claim 8 on which this claim depends. Cho’345 further discloses: wherein the circuit layer (Circuit as shown in figure 6-10) includes:
a semiconductor layer (ACT, fig. 6) disposed on the substrate (101; ¶0094);
a first conductive layer (110, fig. 6) disposed on a first insulating layer (IL1, fig. 6) covering the semiconductor layer (ACT, fig. 6);
a second conductive layer (120, fig. 6) disposed on a second insulating layer (IL2, fig. 6) covering the first conductive layer (110, fig. 6);
a third conductive layer (130, fig. 6) disposed on a third insulating layer (IL3, fig. 6) covering the second conductive layer (120, fig. 6);
a fourth conductive layer (140, fig. 10) disposed on a fourth insulating layer (IL4, fig. 10) covering the third conductive layer (130, fig. 6 and fig. 10); and
a fifth conductive layer (150, fig. 10) disposed on a fifth insulating layer (IL5, fig. 10) covering the fourth conductive layer (140, fig. 10).
Re: Claim 10, Cho’345 discloses all the limitations of claim 9 on which this claim depends. Cho’345 further discloses: wherein the power line is provided at the fifth conductive layer (150, fig. 10) in a first line (DL(2i-1 as shown in figure 15) crossing area positioned between the bending area (BR, fig. 10) and the demultiplexer area (area 60, fig. 4), and a first second line (DL(2i as shown in figure 15) crossing area positioned between the bending area (BR, fig. 4) and the main area (MR, fig. 4).
Re: Claim 14, Cho’345 discloses all the limitations of claim 1 on which this claim depends. Cho’345 further discloses: a first display area (display area (DA) near the left edge of NDA going in DR1 direction, fig. 4) which are positioned in an edge area of the display area (DA, fig. 4) in the second direction (DR2, fig. 4) and in which first data lines (DL, fig. 15) and the pixels connected to the first data lines (DL, fig. 15) are arranged; and
a second display area (center of display area (DA) where layer 60 overlap DA region in DR1 direction, fig. 4) which neighbors to the first display area (display area (DA) near the left edge of NDA going in DR1 direction, fig. 4) in the second direction (DR2, fig. 4) and overlaps a first demultiplexer area (area 60, fig. 4) of the demultiplexer area (area 60, fig. 4) in the first direction (DR1, fig. 4) and in which second data lines (DL, fig. 15) and the pixels connected to the second data lines (DL, fig. 15) are arranged.
Re: Claim 15, Cho’345 discloses all the limitations of claim 14 on which this claim depends. Cho’345 further discloses: wherein the demultiplexer circuits (DEMUX, fig. 2;¶0060) include first demultiplexer circuits (DEMUX, fig. 2) positioned in the first demultiplexer area (area 60, fig. 4),
wherein some of the first lines (DL(2i-1), fig. 2) and the second lines (DL(2i), fig. 2) connected to the first demultiplexer circuits (DEMUX, fig. 2) are connected to the second data lines (DL, fig. 15), and
wherein the others of the first lines (DL(2i-1), fig. 2) and the second lines (DL(2i), fig. 2) connected to the first demultiplexer circuits (DEMUX, fig. 2) are connected to the first data lines (DL, fig. 15) via connection lines passing through a boundary between the first display area (display area (DA) near the left edge of NDA going in DR1 direction, fig. 4) and the second display area (center of display area (DA) where layer 60 overlap DA region in DR1 direction, fig. 4).
Re: Independent Claim 20, Cho ‘345 discloses a substrate (101; ¶0094) including a main area (MR, fig. 4) and a sub-area (SR, fig. 4) positioned on one side of the main area (MR, fig. 4), the main area (MR, fig. 4) including a display area (DA, fig. 4) in which pixels are (PX as shown in figure 4) arranged, and the sub-area (SR, fig. 4) including a demultiplexer area (area 60, fig. 4) and a first line (DL(2i-1 as shown in figure 15) crossing area, a bending area (BR, fig. 4), and a first second line (DL(2i as shown in figure 15) crossing area sequentially disposed along a first direction (DR1, fig. 4) between the demultiplexer area (area 60, fig. 4) and the main area (MR, fig. 4); and
a circuit layer (Circuit as shown in figure 6) disposed on the substrate (101; ¶0094) and including data lines (DL, fig. 15) positioned in the display area (DA, fig. 4) and connected to the pixels, demultiplexer circuits (DEMUX, fig. 2) positioned in the demultiplexer area (area 60, fig. 4) and including first switches (T.sub.DM1, fig. 2) configured to receive a first clock signal (CL1, fig. 2) and second switches (T.sub.DM2, fig. 2) configured to receive a second clock signal (CL2, fig. 2), and a power line (¶0067-68; each pixel include two power voltage line connected to the pixel) positioned in the main area (MR, fig. 4) and the sub-area (SR, fig. 4),
wherein the circuit layer (Circuit as shown in figure 6) further includes:
first lines (DL(2i-1), fig. 2) connecting the first switches (T.sub.DM1, fig. 2) to corresponding data lines (DL, fig. 15) and second lines (DL(2i), fig. 2) connecting the second switches (T.sub.DM2, fig. 2) to corresponding data lines (DL, fig. 15), wherein the first lines (DL(2i-1), fig. 2) and the second lines (DL(2i), fig. 2) extend in the first direction (DR1, fig. 4) in an area other than the first line (DL(2i-1 as shown in figure 15) crossing area and the first second line (DL(2i as shown in figure 15) crossing area.
Cho’345 is silent regarding: shield lines disposed between adjacent first lines (DL(2i-1), fig. 2) and second lines (DL(2i), fig. 2), respectively, and connected to the power line (¶0067-68; each pixel include two power voltage line connected to the pixel).
Cho‘035 discloses a shield lines (SH, fig. 15) disposed between adjacent first lines (DL_E, fig. 15) and the second lines (DL_0, fig. 15) and connected to the power line (¶0018).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a shield lines between two data line since this can prevent occurrence of a coupling capacitor which could cause component failure or signal distortion.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Hyeon et al., US PG pub. 20190140036 A1”) Discloses a display device includes a substrate including a display area and a peripheral area, a pixel area, a data driver, a data divider, and coupling lines that couple the data driver to the data divider. The pixel area includes first pixel lines in a first area of the display area and coupled to first area data lines, and second pixel lines disposed in a second area of the display area and coupled to second area data lines. The data driver outputs data signals corresponding to the first and second pixel lines. The data divider includes first selectors that transfer the data signals corresponding to the first pixel lines to the first area data lines, and second selectors that transfer the data signals corresponding to the second pixel lines to the second area data lines. A distance between adjacent second selectors is shorter than a distance between adjacent first selectors.
* (“Yu et al., US PG pub. 20220123087 A1”) discloses an array substrate and a display device. The array substrate includes: a base substrate including a display area and a peripheral area including a first peripheral area and a corner are; plurality of sub-pixels, data lines, and power lines at the display area; a plurality of control signal lines, data signal input lines, a multiplexing circuit and a first power bus which are at the first peripheral area and the corner area; a plurality of control signal connecting lines electrically connected to the control signal lines, at least partially overlapping with the data signal input lines, and located between the first power bus and the display area; and a plurality of control signal input lines electrically connected to the control signal connecting lines, at least partially overlapping with the first power bus, and on one side of the control signal connecting lines away from the display area.
Allowable Subject Matter
Claim(s) 11-13 and 16-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 11 (and its dependent claim(s) 13), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein the shield lines extend from the bending area to the first line crossing area and the second line crossing area, and wherein each of the shield lines is provided at the fourth conductive layer in the bending area, and is provided at least one of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer, and is electrically connected to the power line in the first line crossing area and the second line crossing area.
Re: Claim 16 (and its dependent claim(s) 17-19), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein the first data lines extend in the first direction in the first display area, wherein the second data lines extend in the first direction in the second display area, and wherein the connection lines extend from the first display area to the second display area along the second direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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