DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim(s) 1-17 is/are objected to because of the following informalities:
With respect to claim 1, “a semiconductor wafer” recited in line 2 of the claim should read “the semiconductor wafer” as it was already introduced in line 1 of the claim. Claims 2-17 which either directly or indirectly depend from claim 1 and which inherit issues of claim 1 are objected to for similar reasons.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 11-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Atendido et al. (JP 201398248, hereinafter “Atendido”, cited on IDS and relying on provided English translation) in view of Motojima et al. (JP 2014207386, hereinafter “Motojima”, cited on IDS and relying on provided English translation).
Regarding claim 1, Atendido teaches in Figs. 1-5 (shown below) and related text, a method for processing a semiconductor wafer (11, Fig.1 and ¶[0019]), the method comprising:
preparing a semiconductor wafer (11, Fig. 1) including a main body (15, Fig. 1 and ¶[0019]), and a rim (21, Fig. 1 and ¶[0020]), the main body (15, Fig. 1) including a first surface (i.e. surface on which devices 13 are formed, Fig. 1 and ¶[0019]) on which a semiconductor element (13, Fig. 1 and ¶[0019]) is formed and a second surface at an opposite side of the first surface (Fig. 1), the rim (21, Fig. 1) having a greater thickness than the main body (15, Fig. 1), the rim surrounding the main body (Fig. 1) in a looped manner (Figs. 2-3 and ¶[0027]) as viewed in a thickness direction of the main body (11, Fig. 1), and the rim (21, Fig. 1) including a projection (i.e. portion of 21 projecting from second surface of the main body, Fig. 1) projecting from the second surface (Fig. 1) of the main body (15, Fig. 1) opposite the first surface in the thickness direction (Fig. 1);
supporting the semiconductor wafer (11, Fig. 1) with a holding tape (T, Fig. 1 and ¶[0027]) adhered to the second surface of the semiconductor wafer (11, Fig. 1);
preparing a base (4, Fig. 4 and ¶[0023]) including a stage (i.e. middle portion of 4, Fig. 4) and an outer portion (i.e. portion of 4 surrounding the middle portion, Fig. 4), the stage including a support surface (e.g. top surface of 4, Fig. 4) that supports the main body (15, Fig. 5), and the outer portion including a head surface at a lower height than the support surface of the stage (Figs. 4 and 5);
setting the semiconductor wafer (11, Fig. 5), which is supported by the holding tape (T, Fig. 5), on the base (4, Fig. 5) so that the main body (15, Fig. 5) is supported by the support surface (e.g. top surface of 4, Fig. 5) of the stage (Fig. 5); and
separating the main body (15, Figs. 1 and 5) and the rim (21, Figs. 1 and 5) by cutting off the rim (21, Figs. 1, 5 and ¶[0044]) in a state in which the main body is supported by the stage (Fig. 5);
wherein the setting the semiconductor wafer (11, Figs. 1 and 5) on the base (4, Figs. 4 and 5) includes setting the semiconductor wafer on the base so that the main body (15, Figs. 1 and 5) is supported by the stage (i.e. middle portion of 4, Figs. 4 and 5) in a state in which the projection is separated from the head surface of the outer portion of the base (i.e. projection of the rim 21 is separated from the outer portion of base 4 by spacer 6, Fig. 5).
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While, Atendido does not explicitly teach that separating the main body and the rim involve cutting an edge portion of the main body, cutting an edge portion of the main body in order to cut off the rim disclosed by Atendido would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention as evidenced by Motojima. Specifically, Motojima, in a similar field of endeavor teaches in Fig. 8 and related text, that separating the main body and the rim, similar to that disclosed by Atendido, can be done by cutting an edge portion of the main body.
Accordingly, since the prior art teaches all of the claimed method steps, using such steps would lead to predictable results, and as such it would have been obvious before the effective filing date of the claimed invention to separate the main body and the rim disclosed by Atendido, by cutting an edge portion of the main body as doing so would amount to nothing more than using a known step to achieve a known result.
Regarding claim 2 (1), the combined teaching of Atendido and Motojima discloses wherein a difference in height between the support surface of the stage (Atendido, i.e. top surface of middle portion of 4, Fig. 4) and the head surface of the outer portion (Atendido, i.e. top surface of outer portion of 4 surrounding the middle portion of 4, Fig. 4) is greater than a projecting length of the projection of the rim (Atendido, i.e. height of 21, Fig. 5).
Regarding claim 3 (1), the combined teaching of Atendido and Motojima discloses wherein:
the holding tape (Atendido, T, Fig. 1) includes an edge portion (Atendido, i.e. outer portion of T, Fig. 1) fixed to a looped frame (Atendido, i.e. annular frame F, Figs. 1-3 and ¶[0021]);
the frame (Atendido, F, Fig. 1) includes an inner wall shaped and sized to allow for accommodation of the semiconductor wafer (Atendido, 11, Fig. 1 and ¶[0021]);
the supporting the semiconductor wafer (Atendido, 11, Fig. 1) with the holding tape (Atendido,T, Fig. 1) includes supporting the semiconductor wafer (Atendido, 11, Fig. 1) with the holding tape (Atendido, T, Fig. 1) that is fixed to the frame (Atendido, F, Fig. 1); and
the setting the semiconductor wafer (Atendido, 11, Fig. 1) on the base (Atendido, 4, Fig. 4) includes setting the semiconductor wafer on the base so that the main body (Atendido, 15, Fig. 1) is supported by the stage (Atendido, i.e. middle portion of 4, Fig. 5) and the frame (Atendido, F, Fig. 5) is supported by the outer portion (Atendido, i.e. outer portion of 4, Fig. 5).
Regarding claim 4 (3), the combined teaching of Atendido and Motojima discloses wherein:
the outer portion of the base (Atendido, 4, Fig. 5) allows a spacer (Atendido, 6, Fig. 5 and ¶[0023]) having a predetermined thickness to be set thereon;
in a state in which the spacer (Atendido, 6, Fig. 5) is set on the outer portion (Atendido, i.e. outer portion of 4, Fig. 5), an upper surface of the spacer (Atendido, 6, Fig. 5) is located at a lower height than the support surface of the stage (Atendido, Fig. 5); and
the setting the semiconductor wafer (Atendido, 11, Fig. 4) on the base (Atendido, 4, Fig. 5) includes setting the semiconductor wafer on the base so that the main body (15, Figs. 1 and 5) is supported by the stage (Atendido, i.e. middle portion of 4, Fig. 5) and the frame (Atendido, F, Fig. 5) is supported by the spacer (Atendido, 6, Fig. 5).
Regarding claim 5 (4), the combined teaching of Atendido and Motojima discloses wherein:
in the separating the main body (Atendido, 15, Fig. 5) and the rim (Atendido, 21, Fig. 5), a gap (Atendido, 28, Figs. 4-5 and ¶[0025]) extends in a direction orthogonal to the head surface of the outer portion of the base (Atendido, i.e. outer surface of the base 4, Figs. 4-5) between the outer portion of the base (Atendido, i.e. outer surface of the base 4, Figs. 4-5) and a rim adhering portion (Atendido, i.e. portion of the holding tape T extending from the bottom of the rim 21 to the frame F, Figs. 1 and 5) of the holding tape (Atendido, T, Figs. 1 and 5 that is adhered to the rim (Atendido, 21, Figs. 1 and 5); and
the spacer (Atendido, 6, Fig. 5) is located outward from the rim (Atendido, 21, Fig. 5) on the outer portion (Atendido, i.e. outer portion of the base 4, Fig. 5).
Regarding claim 11 (4), the combined teaching of Atendido and Motojima discloses wherein:
in the separating the main body (Atendido, 15, Fig. 5) and the rim (Atendido, 21, Fig. 5), a part of the holding tape (Atendido, T, Fig. 5) between the rim and the frame is maintained in an elevated position without being supported by the stage or the spacer (Atendido, i.e. part of the holding tape T above gap 28 is not supported by the stage or the spacer 6, Fig. 5).
Regarding claim 12 (3), the combined teaching of Atendido and Motojima discloses wherein:
the holding tape (Atendido, T, Fig. 5) is circular (Atendido, Figs. 2-3 and ¶[0021]); and
a part of the holding tape (Atendido, T, Fig. 5) between the rim (Atendido, 21, Fig. 5) and the frame (Atendido, F, Fig. 5) has a radial length that is greater than a width of the rim (Atendido, 21, Fig. 5).
Regarding claim 13 (1), the combined teaching of Atendido and Motojima discloses wherein:
the holding tape (Atendido, T, Fig. 5) is a dicing tape (i.e. tape disclosed by Atendido serves the same function as that disclosed by the applicant, accordingly it can be considered a dicing tape); and
in the separating the main body (Atendido, 15, Fig. 5) and the rim (Atendido, 21, Fig. 5), the semiconductor wafer (Atendido, 11, Fig. 5) is cut with a dicing blade (Motojima, 32-1, Fig. 8 and ¶[0021]).
Regarding claim 14 (13), the combined teaching of Atendido and Motojima discloses wherein:
in the separating the main body (Atendido, 15, Fig. 5) and the rim (Atendido, 21, Fig. 5), the semiconductor wafer (Atendido, 11, Fig. 5) is cut in a state in which the stage (Atendido, i.e. middle portion of 4, Fig. 5) is suctioning (¶¶[0025] and [0045]) the holding tape (Atendido, T, Fig. 5) and the outer portion (Atendido, i.e. portion on the outside of 28, Fig. 5) is not suctioning the holding tape (Atendido, T, Fig. 5).
Regarding claim 15 (1), the combined teaching of Atendido and Motojima further discloses separating the rim (Atendido, 21, Fig. 5) from the holding tape (Atendido, T, Fig. 5) after the separating of the main body and the holding tape (Motojima, ¶[0023]).
Regarding claim 16 (15), the combined teaching of Atendido and Motojima further comprises dicing the semiconductor wafer into predetermined chip dimensions after the separating of the rim from the holding tape (Motojima, ¶[0024]).
Regarding claim 17 (16), the combined teaching of Atendido and Motojima discloses wherein the semiconductor wafer is cut from the first surface in both the separating the main body and the rim (Motojima, Fig. 8 and ¶[0021]) and the dicing the semiconductor wafer into predetermined chip dimensions (Motojima, Figs. 9-10 and ¶[0022]).
Allowable Subject Matter
Claim(s) 6-10 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcome the objections stated above.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 6, the prior art of record, alone or in combination, and to the examiner’s knowledge does not teach, disclose, suggest, or render obvious, at least to the skilled artisan, the instant invention regarding a method for processing a semiconductor wafer, particularly characterized by the step of forming a spacer at an outer portion of a base so that the spacer is located only at a position corresponding to a frame to which a holding tape is attached, in combination with all other steps of the method recited in the claim 6. The closest prior art of record to Atendido (JP 201398248) and Motojima (JP 2014207386) fail to disclose the above noted elements of the claim. Claim(s) 7 and 8, which directly depend from claim(s) 6, and which include all of the limitations recited in claim(s) 6, is/are allowed for the similar reasons.
Regarding claim 9, the prior art of record, alone or in combination, and to the examiner’s knowledge does not teach, disclose, suggest, or render obvious, at least to the skilled artisan, the instant invention regarding a method for processing a semiconductor wafer, particularly characterized by the step of forming a spacer between the rim and an outer portion of a base such that during the in the step of separating a main body and a rim of a semiconductor wafer, a gap extends in a direction orthogonal to a head surface of the outer portion of the base between the spacer and a rim adhering portion of the holding tape that is adhered to the rim, in combination with all other steps of the method recited in the claim 9. The closest prior art of record to Atendido (JP 201398248) and Motojima (JP 2014207386) fail to disclose the above noted elements of the claim. Claim(s) 10, which directly depend(s) from claim(s) 9, and which include(s) all of the limitations recited in claim(s) 9 is/are allowed for the similar reasons.
Relevant Prior Art
The following prior art is relevant to the invention but not relied upon in any of the rejections:
Izuka (CN 114256127) teaches in Figs. 1-6 and related text a method for processing a semiconductor wafer, the method comprising: preparing a semiconductor wafer including a main body and a rim, the main body including a first surface on which a semiconductor element is formed and a second surface at an opposite side of the first surface, the rim having a greater thickness than the main body, the rim surrounding the main body in a looped manner as viewed in a thickness direction of the main body, and the rim including a projection projecting from the second surface of the main body opposite the first surface in the thickness direction (Fig. 1B), supporting the semiconductor wafer with a holding tape (23, Fig. 1B) adhered to the second surface of the semiconductor wafer (Fig. 1B), preparing a base (16, Fig. 5) including a stage and an outer portion, the stage including a support surface that supports the main body, and the outer portion including a head surface at a lower height than the support surface of the stage; setting the semiconductor wafer, which is supported by the holding tape, on the base so that the main body is supported by the support surface of the stage (Fig.6), and separating the main body and the rim by cutting an edge portion of the main body in a state in which the main body is supported by the stage (Fig. 6), wherein the setting the semiconductor wafer on the base includes setting the semiconductor wafer on the base so that the main body is supported by the stage in a state in which the projection is separated from the head surface of the outer portion of the base (Fig. 6).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANETA B CIESLEWICZ whose telephone number is 303-297-4232. The examiner can normally be reached M-F 8:30 AM - 2:30 PM.
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/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893