Prosecution Insights
Last updated: July 05, 2026
Application No. 18/512,078

OPTICAL CONNECTOR UNIT FOR A PHOTONIC ASSEMBLY AND METHODS FOR FORMING THE SAME

Non-Final OA §102§103§DOUBLEPATENT
Filed
Nov 17, 2023
Priority
Jun 20, 2023 — provisional 63/509,089 +1 more
Examiner
CONNELLY, MICHELLE R
Art Unit
2874
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
817 granted / 1023 resolved
+11.9% vs TC avg
Moderate +13% lift
Without
With
+13.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
30 currently pending
Career history
1056
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
77.4%
+37.4% vs TC avg
§102
11.0%
-29.0% vs TC avg
§112
7.9%
-32.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1023 resolved cases

Office Action

§102 §103 §DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The prior art documents submitted by applicant in the Information Disclosure Statement filed on December 29, 2024 have all been considered and made of record except for Foreign Patent Document 3, which has been lined-through because a copy of the reference is not in the file (note the attached copy of form PTO-1449). Drawings Sixty-nine (69) sheets of drawings were filed on November 17, 2023 and one (1) replacement sheet of drawings was filed on December 5, 2023. The drawings have been accepted by the examiner. Specification Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Inventorship This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-7, 10, and 16-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,554,080 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 at least disclose or suggest all of the limitations of claims 1-7, 10, and 16-18 of the present application. Regarding claim 1; Claim 1 or claim 10 of U.S. Patent No. 12,554,080 B2 at least discloses or suggests a photonic assembly (see claim 1, column 36, lines 57; and see claim 10, column 38, line 4) comprising: a composite die including a photonic integrated circuits (PIC) die and an electronic integrated circuits (EIC) die, the PIC die comprising waveguides and photonic devices therein, and the EIC die comprising semiconductor devices therein (see claim 1, column 36, lines 58-62; and see claim 10, column 38, lines 5-10); and an optical connector unit proximal to a top surface of the composite die and comprising a first connector-side mirror reflector and a first transition edge coupler, wherein the first connector-side mirror reflector is configured to change a beam direction between a vertically-extending beam path through the composite die and a horizontally-extending beam path through the first transition edge coupler (see claim 1, column 36, line 63, through column 37, line 3; and see claim 10, column 38, lines 11-17). Regarding claim 2; Claim 1 or claim 11 of U.S. Patent 12,554,080 B2 at least discloses or suggests he photonic assembly of Claim 1, wherein the optical connector unit comprises an optical connector die that is attached to a top surface of the composite die (see claim 1, column 36, lines 64-66, wherein the provision of a connector die, i.e. substrate, on which the mirror and edge coupler are formed is within the level of ordinary skill in the art; see claim 11). Regarding claim 3; Claims 1 or 11 teach or suggest the photonic assembly of Claim 2 (see above discussion with respect to claim 2), wherein further comprising an optical glue portion bonding a bottom surface of the optical connector die to the top surface of the composite die (it’s within the level or ordinary skill in the art to provide an optical glue, such as an optical adhesive, an optical epoxy, etc. to secure optical connector dies to desired locations of photonic assemblies. Regarding claim 4; Claim 1 teaches or suggests the photonic assembly of Claim 3 (see above discussion with respect to claim 2), and claim 2 further teaches or suggests that the assembly further comprises an encapsulation cover having a horizontally-extending portion overlying the optical connector die and a vertically-extending portion that is attached to a sidewall of the optical connector die through the optical glue portion (see claim 2, column 37, lines 6-11). Regarding claim 5; claim 3, dependent from claim 1, discloses wherein: the composite die comprises a support semiconductor substrate interposed between the PIC die and the optical connector unit; and the vertically-extending beam path vertically extends through the support semiconductor substrate (see claim 3, column 37, lines 12-17). Regarding claim 6; claim 3, dependent from claim 1, further defines an optically transparent dielectric layer overlying a top surface of the support semiconductor substrate, wherein the optical connector unit is located over the optically transparent dielectric layer (see claim 3, column 37, lines 18-22). Regarding claim 7; it is within the level of ordinary skill in the art to embed optical connector units within optically transparent dielectric layers for the purpose of providing protection to the optical connectors and isolating the optical connectors from the environment surrounding the dielectric layer encapsulating the connectors. Regarding claim 10; claim 5 teaches wherein the optical connector unit comprises: a dielectric matrix layer embedding the first connector-side mirror reflector and the first transition edge coupler; a first spacer plate located over the first connector-side mirror reflector and more distal from the composite die than the first connector-side mirror reflector; and a second spacer plate interposed between the composite die and the dielectric matrix layer (see claim 5, column 37, lines 28-38). Regarding claim 16; Claim 16 of U.S. Patent 12,554,080 discloses a method of forming a photonic assembly, the method comprising: forming an assembly comprising a photonic integrated circuits (PIC) die and an electronic integrated circuits (EIC) die, the PIC die comprising waveguides and photonic devices therein, and the EIC die comprising semiconductor devices therein (see claim 16, column 38, lines 42-48); and forming an optical connector unit comprising a first connector-side mirror reflector and a first transition edge coupler on the assembly, whereby a composite die comprising the PIC die and the EIC die is formed, wherein the first connector-side mirror reflector is configured to change a beam direction between a vertically-extending beam path through the composite die and a horizontally-extending beam path through the first transition edge coupler (see claim 16, column 38, lines 49-56). Regarding claim 17; Claim 17 of U.S. Patent 12, 554,090 defines wherein the optical connector unit comprises an optical connector die that is attached to a top surface of the composite die (see claim 17, column 38, lines 62-64). Regarding claim 18; the provision of encapsulation layers and the practice of attaching optical substrates with optical glue are both well known in the optical arts for the purpose of protecting optical dies/couplers and securing the location of optical dies/couplers. Therefore, a person of ordinary skill in the art would have found it obvious to practice the method of claim 17, further comprising attaching an encapsulation cover to the optical connector die, wherein the encapsulation cover has a horizontally-extending portion overlying the optical connector die and a vertically-extending portion that is attached to a sidewall of the optical connector die through an optical glue portion. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 16, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (US 2021/0167016 A1). Regarding claims 1 and 2; Lu et al. discloses a photonic assembly (see Figure 3) comprising: a composite die including a photonic integrated circuits (PIC) die (PIC 30; see Figure 3 and paragraph 20) and an electronic integrated circuits (EIC) die (EIC 60; see Figure 3 and paragraph 20), the PIC die (30) comprising waveguides and photonic devices therein (see paragraph 18), and the EIC die comprising semiconductor devices therein (see paragraph 18); and an optical connector unit (coupler 34; see Figure 3 and paragraph 30) proximal to a top surface of the composite die (see Figure 3) and comprising a first connector-side mirror reflector (reflector 38A) and a first transition edge coupler (the body of coupler 34 transitions to an optical fiber 36 at an edge thereof), wherein the first connector-side mirror reflector (38B) is configured to change a beam direction between a vertically-extending beam path through the composite die and a horizontally-extending beam path through the first transition edge coupler (see Figure 3 and paragraph 30); wherein the optical connector unit (34) comprises an optical connector die that is attached to a top surface of the composite die (see Figure 3). Regarding claims 16 and 17; Lu et al. discloses a method of forming a photonic assembly (see Figure 3), the method comprising: forming an assembly comprising a photonic integrated circuits (PIC) die (PIC 30) and an electronic integrated circuits (EIC) die (EIC 60), the PIC die comprising waveguides and photonic devices therein (see paragraph 18), and the EIC die comprising semiconductor devices therein (see paragraph 18); and forming an optical connector unit (34) comprising a first connector-side mirror reflector (38B) and a first transition edge coupler (the body of coupler 34 transitions to an optical fiber 36 at an edge thereof) on the assembly (see Figure 3), whereby a composite die (see Figure3) comprising the PIC die (30) and the EIC die (60) is formed, wherein the first connector-side mirror reflector (38B) is configured to change a beam direction between a vertically-extending beam path through the composite die and a horizontally-extending beam path through the first transition edge coupler (body of coupler 34); wherein the optical connector unit (30) comprises an optical connector die that is attached to a top surface of the composite die (see Figure 3). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2021/0167016 A1). Regarding claim 3; Lu et al. discloses the photonic assembly of Claim 2 as applied above, but does not disclose that an optical glue portion bonding a bottom surface of the optical connector die to the top surface of the composite die. The examiner takes Official notice that optical adhesive (i.e. optical glue) is known to be used to attached optical connectors to photonic assembly package structure. Before the effective filing date of the present invention, a person of ordinary skill in the art would have found it obvious to provide an optical glue portion bonding a bottom surface of the optical connector die (34) to the top surface of the composite die (see Figure 3) for the purpose of securing the optical connector die (34) to maintain optical alignment between the PIC (30) of the composite die and the optical connector and minimize optical loss. Allowable Subject Matter Claims 4-7, 10, and 18 are rejected under Non-Statutory Double Patenting above, but would be allowable if the Non-Statutory Double Patenting rejection were overcome and if rewritten in independent form including all of the limitations the base claim and any intervening claims. Claims 8, 9, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 11-15 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, which is the most relevant prior art known, does not disclose or render obvious: the photonic assembly defined by claim 4, further comprising an encapsulation cover having a horizontally-extending portion overlying the optical connector die and a vertically-extending portion that is attached to a sidewall of the optical connector die through the optical glue portion in combination with all of the limitations of base claim 1 and all of the limitations of intervening claims 2 and 3; the photonic assembly defined by claim 8, wherein the optical connector unit comprises a support matrix that is attached to the first connector-side mirror reflector and a first transition edge coupler, and the support matrix comprises a plurality of receptacle cavities therein in combination with all of the limitations of base claim 1; or the photonic assembly defined by claim 5, wherein the composite die comprises a support semiconductor substrate interposed between the PIC die and the optical connector unit, and the vertically-extending beam path vertically extends through the support semiconductor substrate in combination with all of the limitations of base claim 1; or the photonic assembly defined by claim 10, wherein the optical connector unit comprises: a dielectric matrix layer embedding the first connector-side mirror reflector and the first transition edge coupler; a first spacer plate located over the first connector-side mirror reflector and more distal from the composite die than the first connector-side mirror reflector; and a second spacer plate interposed between the composite die and the dielectric matrix layer, in combination with all of the limitations of base claim 1; or the method defined by claim 18, further comprising attaching an encapsulation cover to the optical connector die, wherein the encapsulation cover has a horizontally-extending portion overlying the optical connector die and a vertically-extending portion that is attached to a sidewall of the optical connector die through an optical glue portion in combination with all of the limitations of base claim 16 and all of the limitations of intervening claim 17; or the method defined by claim 19, wherein the composite die comprises an optically transparent dielectric layer overlying a top surface of a support semiconductor substrate; and the optical connector unit is formed within the optically transparent dielectric layer in combination with all of the limitations of base claim 16; or the method defined by claim 20, wherein the optical connector unit is formed by attaching the first connector-side mirror reflector and a first transition edge coupler to a support matrix; and forming a plurality of receptacle cavities from a sidewall of the support matrix in combination with all of the limitations of base claim 16 Claims 6 and 7 are allowable by virtue of dependency from claim 5, and claim 9 is allowable by virtue of dependency from claim 8. The prior art of record, which is the most relevant prior art known, does not disclose or render obvious a photonic assembly, as defined by claim 11, comprising: a composite die including a photonic integrated circuits (PIC) die, an electronic integrated circuits (EIC) die, and a support semiconductor substrate overlying the PIC die and the EIC die, the PIC die comprising an optical deflector; and an optical connector unit proximal to a top surface of the composite die and comprising a first connector-side mirror reflector and a first transition edge coupler, wherein the first connector-side mirror reflector is configured to change a beam direction between a vertically-extending beam path extending between the optical deflector and the first connector-side mirror reflector and through the support semiconductor substrate and a first horizontally-extending beam path through the first transition edge coupler. Claims 12-15 are allowable by virtue of their dependency from claim 11. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Zhang et al. (US 2021/0132309 A1) discloses a composite die with an optical coupler attached to a top surface (see the entire disclosure), and teaches that optical adhesives are known to be used to attached connectors to the composite structure (package structure; see paragraph 86; see Figure 6A); Liu et al. (US 2024/0192453 A1), see entire document; Mayukh et al. (US 11,906,802 B2), see entire document; Kim et al. (US 2023/0204879 A1), see entire document; Kim et al. (US 2023/0194778 A1), see entire document; and Karhade et al. (US 2023/0092821 A1), see entire document. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHELLE R CONNELLY whose telephone number is (571)272-2345. The examiner can normally be reached Monday-Friday, 9 AM to 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHELLE R CONNELLY/Primary Examiner, Art Unit 2874
Read full office action

Prosecution Timeline

Nov 17, 2023
Application Filed
Apr 03, 2026
Non-Final Rejection mailed — §102, §103, §DOUBLEPATENT (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
93%
With Interview (+13.4%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1023 resolved cases by this examiner. Grant probability derived from career allowance rate.

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