DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-20 in the reply filed on 6/2/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 21-25 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected process of making a product, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/2/206.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1 ll. 2-3, it is indefinite as to whether the “second metallization (M2) layer on which the M1 layer is disposed” means that the M1 is on a higher metal level than the M2 layer or the M2 layers is on a higher metal level than the M1 layer. For purposes of examination the later interpretation will be used. Claims 2-7 do not remedy the deficiencies of claim 1.
In claim 8 ll. 2-3, it is indefinite as to whether the “second metallization (M2) layer on which the M1 layer is disposed” means that the M1 is on a higher metal level than the M2 layer or the M2 layers is on a higher metal level than the M1 layer. For purposes of examination the later interpretation will be used. In claim 8 ll. 3-4, it is indefinite as to whether the “multiple additional metallization layers on or over which the M2 layer is disposed” means that the M2 layer is on a higher metal level than the additional metallization layers or the additional metallization layers on a higher metal level than the M2 layer. For purposes of examination the former interpretation will be used. Claims 9-14 do not remedy the deficiencies of claim 8.
In claim 15 ll. 2-3, it is indefinite as to whether the “second metallization (M2) layer on which the M1 layer is disposed” means that the M1 is on a higher metal level than the M2 layer or the M2 layers is on a higher metal level than the M1 layer. For purposes of examination the later interpretation will be used. In claim 8 ll. 3-4, it is indefinite as to whether the “multiple additional metallization layers on or over which the M2 layer is disposed” means that the M2 layer is on a higher metal level than the additional metallization layers or the additional metallization layers on a higher metal level than the M2 layer. For purposes of examination the former interpretation will be used. Claims 16-20 do not remedy the deficiencies of claim 15.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guillorn (US 10,096,607).
With regard to claim 1, figs. 4-6 of Guillorn discloses a static random access memory (SRAM) structure 400, comprising: a wafer comprising a first metallization (M1) layer (M1 in fig. 6) and a second metallization (M2) layer (M2 in fig. 6) on which the M1 layer (M1 in fig. 6) is disposed; and a fully functional SRAM cell 400 comprising circuitry using a maximum of the M1 layer (M1, fig. 6) and the M2 layer (M1, fig. 6).
With regard to claim 2, figs. 3-6 of Guillorn discloses that the SRAM cell 400 comprises SRAM circuitry, a peripheral circuit 170 and a logic circuit 160 using the maximum of the M1 layer (M1, fig. 6) and the M2 layer (M2, fig. 6).
With regard to claim 3, figs. 3-6 of Guillorn discloses that of the circuitry comprises: word line WL and bit line BL1 circuitry limited to the M1 layer (M1) and the M2 (M2) layer; and power distribution circuitry 630 limited to the M2 layer (M2).
With regard to claim 4, figs. 3-6 of Guillorn discloses that the word line and bit line circuitry are spread horizontally outwardly from the SRAM cell.
With regard to claim 5, figs. 3-6 of Guillom disclose that the bit lines (BL1) of the bit line circuitry are oriented vertically on the M1 layer (M1) and word lines 510 of the word line circuitry (WL) are limited to the M2 layer (M2).
With regard to claim 6, figs. 3-6 of Guillom disclose that the power distribution circuitry 530 is disposed proximate to the SRAM cell 400.
With regard to claim 7, figs. 3-6 of Guillom disclose that an output of the SRAM cell 400 is routed locally BL1 on the M1 layer (M1) and then routed to the M2 layer (M2).
Claims 8-19 are rejected under 35 U.S.C. 102 as being anticipated by Liaw (US 10,043,571).
With regard to claim 8, figs. 4-5B of Liaw disclose that a static random access memory (SRAM) structure 10A, comprising: a wafer comprising a first metallization layer M1, a second metallization (M2) layer 2 on which the M1 layer M1 is disposed and multiple additional metallization layers on or over which the M2 layer (M3, M4) is disposed; and a fully functional SRAM cell 400 comprising circuitry using only the M1 layer and the M2 layer (M1, M2).
With regard to claim 9, figs. 4-5B of Liaw discloses that the SRAM cell 400 comprises SRAM circuitry, a peripheral circuit PG-1 and a logic circuit PD-1 using only the M1 layer (M1) and the M2 layer (M2).
With regard to claim 10, figs. 4-5B of Liaw discloses that the circuitry comprises: word line WL1 and bit line BL1 circuitry limited to the M1 layer (M1) and the M2 layer (M2); and power distribution circuitry Vss3 limited to the M2 layer (M2).
With regard to claim 11, figs. 4-5B of Liaw discloses that the word line WL1 and bit line BL1 circuitry are spread horizontally (X, Y) outwardly from the SRAM cell 10A.
With regard to claim 12, figs. 4-5B of Liaw discloses that bit lines of the bit line circuitry are oriented vertically 448-2 on the M1 layer (M1) and word lines WL1 of the word line circuitry 460-2 are limited to the M2 layer (M2).
With regard to claim 13, figs. 4-5B of Liaw discloses that the power distribution circuitry Vss1 is disposed proximate to the SRAM cell 10A.
With regard to claim 14, figs. 4-5B of Liaw discloses that an output BL1 of the SRAM cell 10A is routed locally on the M1 (M1) layer BL1 and then routed 448-2 to the M2 layer 460-1.
With regard to claim 15, figs. 4-5B of Liaw discloses that a static random access memory (SRAM) structure 10A, comprising: a wafer comprising a first metallization (M1) layer (M1), a second metallization (M2) layer (M2) on which the M1 layer (M1) is disposed and multiple additional metallization layers (M3, M4) on or over which the M2 layer (M2) is disposed; and a fully functional SRAM cell 10A comprising: word line WL1 and bit line circuitry BL1 limited to the M1 layer (M1) and the M2 layer (M2); and power distribution circuitry Vss3 limited to the M2 layer (M2).
With regard to claim 16, figs. 4-5B of Liaw discloses that the SRAM cell comprises SRAM circuitry, a peripheral circuit PG-1 and a logic circuit PD-1 limited to the M1 layer (M1) and the M2 layer (M2).
With regard to claim 17, figs. 4-5B of Liaw discloses that the word line WL1 and bit line BL1 circuitry are spread horizontally (X, Y) outwardly from the SRAM cell 10A.
With regard to claim 18, figs. 4-5B of Liaw discloses that bit lines of the bit line circuitry are oriented vertically 448-2 on the M1 layer (M1) and word lines WL1 of the word line circuitry 460-2 are limited to the M2 layer (M2).
With regard to claim 19, figs. 4-5B of Liaw discloses that the power distribution circuitry Vss1 is disposed proximate to the SRAM cell 10A.
With regard to claim 20, figs. 4-5B of Liaw discloses that an output BL1 of the SRAM cell 10A is routed locally on the M1 (M1) layer BL1 and then routed 448-2 to the M2 layer 460-1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
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