DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 1-9 and 15-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention and/or Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 27 March 27 2026. Applicants are reminded to indicate the withdrawn status of claims 1-9 and 15-17 in their next submission of a claim listing. The Restriction and Election Requirements are deemed proper and made final.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10, 11, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US20170125378A1) in view of Mostovoy et al. (US20180174996A1).
Regarding claim 10, Park teaches in Figs. 6A-6C a semiconductor package, comprising:
a package substrate (300) {[0152]};
a processor chip (500/600) on the package substrate (300) {[0155]};
a first stacked structure (100a) on the package substrate (300), the first stacked structure (100a) including offset-stacked first memory chips (101) {[0087, 0152]}; and
a second stacked structure (200a) on the package substrate (300), the second stacked structure (200a) including offset-stacked second memory chips (201) {[0087, 0152]},
wherein the processor chip (500/600) includes a first area (e.g., area of periphery of upper surface to which wires are attached) and a second area (e.g., area of central portion of upper surface), the first area having four sides of the upper surface of the processor chip (500/600) that surround the second area.
Park does not teach:
the package substrate including substrate pads;
the processor chip including chip pads on an upper surface of the processor chip; and
the chip pads being on the first area and being arranged in a line on at least two of the four sides of the upper surface in a direction parallel to the at least two of the four sides of the upper surface.
In an analogous art, Mostovoy teaches in Fig. 3 a package substrate (110) including substrate pads (122) {[0023]}; a processor chip (104) including chip pads (130 and/or 134) on an upper surface of the processor chip (104) {[0015, 0029]}; the chip pads (130 and/or 134) being on a first area (e.g., area of periphery of upper surface of 104 to which wires are attached) and being arranged in a line on at least two of the four sides of the upper surface in a direction parallel to the at least two of the four sides of the upper surface. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s semiconductor package based on the teachings of Mostovoy, to achieve the above-identified subject matter, so the die bond pads [of the processor chip] … may be wire bonded to contact pads … on substrate … via wire bonds … to establish narrow I/O electrical connections between the … [processor] chip … and the substrate. Mostovoy [0029]. Moreover, all the claimed elements (e.g., package substrate, substrate pads, processor chip, chip pads) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Mostovoy) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 11, Park as modified by Mostovoy teaches the semiconductor package as claimed in claim 10, but Park does not teach wherein the chip pads include:
first chip pads arranged on a first side of the upper surface of the processor chip in a line along the first side; and
second chip pads arranged on a second side of the upper surface of the processor chip in a line along the second side.
Mostovoy teaches in Fig. 3 and paragraph [0028] the chip pads (130, 134) include: first chip pads (130) arranged on a first side of the upper surface of the processor chip (104) in a line along the first side; and second chip pads (134) arranged on a second side of the upper surface of the processor chip (104) in a line along the second side. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s semiconductor package as modified by Mostovoy based on the further teachings of Mostovoy, to achieve the above-identified subject matter, so: (1) to establish wide I/O electrical connections between each semiconductor die in the stack … and the … [processor] chip; and (2) the die bond pads [of the processor chip] … may be wire bonded to contact pads … on substrate … via wire bonds … to establish narrow I/O electrical connections between the … [processor] chip … and the substrate. Mostovoy [0028, 0029]. Moreover, all the claimed elements (e.g., processor chip, chip pads) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Mostovoy) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 18, Park as modified by Mostovoy teaches the semiconductor package as claimed in claim 10, and Park further teaches wherein the second stacked structure (200a) is spaced apart from the first stacked structure (100a) with the processor chip (500/600) therebetween and is mounted on the package substrate (300) {[0155]}.
Regarding claim 19, Park as modified by Mostovoy teaches the semiconductor package as claimed in claim 10, and Park further teaches wherein the processor chip (500/600) is attached to the package substrate (300) by an adhesive member (603) {[0157]}.
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Mostovoy as applied to claim 10 above, and further in view of Chen et al. (US20090057902A1).
Regarding claim 12, Park as modified by Mostovoy teaches the semiconductor package as claimed in claim 11, but Park does not teach wherein the substrate pads include first substrate pads and second substrate pads,
the semiconductor package further comprising:
first wires electrically connecting at least some of the first substrate pads to the first chip pads; and
second wires electrically connecting at least some of the second substrate pads to the second chip pads.
In an analogous art, Chen teaches in Figs. 1 and 2 and paragraph [0017] substrate pads (15) include first substrate pads (left side 15) and second substrate pads (right side 15), first wires (left side 9) electrically connecting at least some of the first substrate pads (left side 15) to first chip pads (left side 17); and second wires (right side 9) electrically connecting at least some of the second substrate pads (right side 15) to second chip pads (right side 17). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s semiconductor package based as modified by Mostovoy on the teachings of Chen, to achieve the above-identified subject matter, so signal contact pads … on [a] package substrate … deliver and/or receive electrical signals to/from … [a processor] chip … via signal lines. Chen [0017]. Moreover, all the claimed elements (e.g., substrate pads, wires, chip pads) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chen) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 13, Park as modified by Mostovoy and Chen teaches the semiconductor package as claimed in claim 12, and Park further teaches further comprising:
third wires (416) connecting at least some of the first substrate pads (as modified by Chen’s left side 15) to the first stacked structure (100a) {Fig. 6B; [0158]}; and
fourth wires (416) connecting at least some of the second substrate pads (as modified by Chen’s right side 15) to the second stacked structure (200a) {Fig. 6C; [0157]}.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Mostovoy and Chen as applied to claim 10 above, and further in view of Jeong et al (US20210249382A1).
Regarding claim 14, Park as modified by Mostovoy and Chen teaches the semiconductor package as claimed in claim 13, but Park does not teach wherein:
among the first substrate pads, one first substrate pad connected to one of the first wires and another first substrate pad connected to one of the third wires are connected to each other by first internal wires, and
among the second substrate pads, one second substrate pad connected to one of the second wires and another second substrate pad connected to one of the fourth wires are connected to each other by second internal wires.
In an analogous art, Jeong teaches in Fig. 5 and paragraphs [0061, 0073] among substrate pads (120), one substrate pad (e.g., 3rd 120 from left side of 200) connected to one (e.g., 3rd 230 from left side of 200) of first wires (e.g., 230s) and another substrate pad (e.g., 2nd 120 from right side of drawing) connected to one (e.g., 430) of the third wires (e.g., 430, 530, and/or 630) are connected to each other by first internal wires (e.g., vertical and horizontal wire portions of 114 between 3rd 120 from left side of 200 to 2nd 120 from right side of drawing). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s semiconductor package based as modified by Mostovoy and Chen on the teachings of Jeong – to include: (1) among the first substrate pads, one first substrate pad connected to one of the first wires and another first substrate pad connected to one of the third wires are connected to each other by first internal wires, and (2) among the second substrate pads, one second substrate pad connected to one of the second wires and another second substrate pad connected to one of the fourth wires are connected to each other by second internal wires – to provide channels for electrical connection between the … [processor] chip … and memory chips. Jeong [0057]. Moreover, all the claimed elements (e.g., substrate pads, wires) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Jeong) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Chen and Jeong.
Regarding claim 20, Park teaches in Figs. 6A-6C a semiconductor package, comprising:
a package substrate (300) {[0152]};
a processor chip (500) on the package substrate (300) {[0155]};
a first stacked structure (100a) on the package substrate (300), the first stacked structure (100a) including offset-stacked first memory chips (101) {[0087, 0152]}; and
a second stacked structure (200a) on the package substrate (300), the second stacked structure (200a) including offset-stacked second memory chips (201) {[0087, 0152]}, wherein:
the processor chip (500) includes a first area (e.g., area of periphery of upper surface to which wires are attached) and a second area (e.g., area of central portion of upper surface), the first area having four sides of the upper surface of the processor chip (500) and surrounding the second area.
Park does not teach:
the package substrate including first substrate pads and second substrate pads;
the processor chip including first chip pads and second chip pads on an upper surface of the processor chip; and
the first chip pads and the second chip pads are on the first area and are arranged in a line along at least two of the four sides of the upper surface in a direction parallel to the at least two of the four sides of the upper surface.
In an analogous art, Chen teaches in Figs. 1 and 2 and paragraph [0017] a package substrate (1) including first substrate pads (left side 15) and second substrate pads (left side 15); a processor chip (3) including first chip pads (left side 9) and second chip pads (right side 9) on an upper surface of the processor chip (3); the first chip pads (left side 9) and the second chip pads (right side 9) are on a first area (peripheral area including 9s) and are arranged in a line along at least two of the four sides of the upper surface in a direction parallel to the at least two of the four sides of the upper surface. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s semiconductor package based on the teachings of Chen, to achieve the above-identified subject matter, so the package substrate … deliver[s] and/or receive[s] electrical signals to/from … [the processor] chip … via signal lines. Chen [0017]. Moreover, all the claimed elements (e.g., package substrate, substrate pads, processor chip, chip pads) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chen) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Park as modified by Chen does not teach the processor chip and the first stacked structure are wire-bonded to each other through the first substrate pads, and the processor chip and the second stacked structure are wire-bonded to each other through the second substrate pads.
However, Park teaches in an embodiment disclosed by Fig. 7 and paragraphs [0163, 0164] that a single processor chip may be substituted for the two processor chips (500, 600) disclosed with respect to the embodiment illustrated by Figs. 6A-6C. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s semiconductor package as modified by Chen based on the further teachings of Park – such that the two processor chips of Figs. 6A-6C are replaced by a single processor chip – to reduce the manufacturing resources (e.g., manufacturing operations, materials, footprint, time, etc). Moreover, all the claimed elements (e.g., processor chip) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Park) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Still further, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E). Still further, making separate components integral is a matter of obvious engineering choice. MPEP §2144.04(V)(B).
Jeong teaches in Fig. 5 and paragraph [0075] a processor chip (200) and a stacked structure (600) are wire-bonded (through e.g., 630) to each other through substrate pads (120). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s semiconductor package as modified by Chen based on the teachings of Jeong – such that the processor chip and the first stacked structure are wire-bonded to each other through the first substrate pads, and the processor chip and the second stacked structure are wire-bonded to each other through the second substrate pads – so the processor chip may be electrically connected to the memory chips through the substrate pads. Jeong [0075, 0125]. Moreover, all the claimed elements (e.g., processor chip, stacked structure, wire-bonded, substrate pads) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Jeong) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al. (US20230005884A1) teaches a semiconductor package including a package substrate including first and second bonding pads, third bonding pads spaced apart from the first bonding pads, and fourth bonding pads spaced apart from the second bonding pads; a first chip stack including first chips stacked on the package substrate, each first chip including first signal pads and first power/ground pads alternately arranged; a second chip stack including second chips stacked on the first chip stack, each second chip including second signal pads and second power/ground pads alternately arranged; first lower wires that connect the first signal pads to the first bonding pads; second lower wires that connect the first power/ground pads to the second bonding pads; first upper wires that connect the second signal pads of the second chips to the third bonding pads; and second upper wires that connect the second power/ground pads of the second chips to the fourth bonding pads.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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