DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statements (IDS) filed on:
22 November 2023
20 December 2023
21 December 2023
22 March 2024
30 July 2024
30 December 2025
The references cited on the PTOL 1449 forms have been considered.
There was also an Information Disclosure Statement (IDS) submitted in the instant application with references directed towards unrelated subject matter intended for a different application (18/804,596) filed on 22 November 2023 (6 pages). The references cited on that PTOL 1449 form have been considered, however, none are relevant to the applicant’s invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Blanchard et al. (U.S. Patent Application Publication 2015/0214055).
Referring to Claim 1, Blanchard teaches a method for fabricating a thin bidirectional bipolar junction transistor device, comprising: forming a first base region (305) and a first emitter/collector region (303) on a first side (321) of a first thick semiconductor wafer (301; Fig. 3A; par. 34 and 35); removing a portion of the first thick semiconductor wafer (301) to produce a first thin semiconductor wafer (301; Fig. 3C to Fig. 3D; par. 26, 42, 58, 59 and 91); forming a second base region (305) and a second emitter/collector region (303) on a second side (323) of the first thin semiconductor wafer opposite the first side (Fig. 3E; par. 43, 44); producing a second thin semiconductor wafer (319; silicon high-temperature handle wafer; par. 40); and bonding (via adhesive 337) the first thin semiconductor wafer to the second thin semiconductor wafer (Fig. 3H; par. 46).
Referring to Claim 4, Blanchard further teaches wherein removing the portion of the first thick semiconductor wafer (301) further includes grinding the second side (323) of the first thick semiconductor wafer (301; Fig. 3C to Fig. 3D; par. 26, 42, 58 and 59).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard et al. (U.S. Patent Application Publication 2015/0214055) in view of Ravi (U.S. Patent Application Publication 2002/0004287).
Referring to Claim 7, Blanchard teaches the limitations of claim 1, wherein an initial thickness of the first thick semiconductor wafer is 400 micrometers for example, and wherein a reduced thickness of the first thin semiconductor wafer is in a range of less than 80 micrometers for example (par. 26, 42, 89 and 90).
Blanchard discloses the claimed invention except for wherein a thickness of the first thick semiconductor wafer is at least 750 micrometers, and wherein a thickness of the first thin semiconductor wafer is in a range of about 80 micrometers to about 110 micrometers, per se.
Ravi teaches the well-known use of having an initial wafer thickness of 750 micrometers and thinning the wafer to a more suitable thickness of 25 to 100 micrometers (par. 6)
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide an initial semiconductor wafer of at least 750 micrometers and thin that semiconductor wafer to about 80 micrometers to about 110 micrometers in order to achieve the final desired device thickness before processing begins on the second side (par. 26) suitable for forming semiconductor devices, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Allowable Subject Matter
Claims 2, 3, 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 8-20 are allowable.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, the prior art of record alone or in combination neither teaches nor makes obvious the invention of wherein producing the second thin semiconductor wafer further includes: forming a third base region and a third emitter/collector region on a third side of a second thick semiconductor wafer, removing a portion of the second thick semiconductor wafer to produce the second thin semiconductor wafer, and forming a fourth base region and a fourth emitter/collector region on a fourth side of the second thin semiconductor wafer opposite the third side in combination with all of the limitations of Claim 1 and 2. Claim 3 includes the limitations of claim 2.
Regarding Claim 5, the prior art of record alone or in combination neither teaches nor makes obvious the invention of wherein forming the second base region and the second emitter/collector region on the second side of the first thin semiconductor wafer further includes activating, without the diffusion process, the first-conductivity-type dopant and the second conductivity-type dopant introduced into different regions on the second side of the first thin semiconductor wafer in combination with all of the limitations of Claim 1 and 5. Claim 6 includes the limitations of claim 1.
Regarding Claim 8, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the method for fabricating a thin bidirectional bipolar junction transistor device, comprising: activating, without the diffusion process, the first-conductivity-type dopant and the second conductivity-type dopant introduced into different regions on the second side of the first semiconductor wafer; activating, with the diffusion process, the first-conductivity-type dopant and the second conductivity-type dopant introduced into different regions on a first side of a second semiconductor wafer; activating, without the diffusion process, the first-conductivity-type dopant and the second conductivity-type dopant introduced into different regions on the second side of the second semiconductor wafer in combination with all of the limitations of Claim 8.
Claims 9-13 include the limitations of claim 8.
Regarding Claim 14, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the thin bidirectional bipolar junction transistor device, comprising: wherein the first backside junction is thinner than the first front side junction; and wherein the second backside junction is thinner than the second front side junction in combination with all of the limitations of Claim 14. Claims 15-20 include the limitations of claim 14.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896