0DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 3-4, 14-15, and 17 are objected to because of the following informalities:
Claim 3 recites “wherien” (line 1) which should be replaced with “wherein”, to improve claim language.
Claim 4 recites “a the first drain electrode” (line 3) which should be replaced with “the first drain electrode”, to improve claim language.
Claim 14 recites “satisifed” (line 2) which should be replaced with “satisfied”, to improve claim language.
Claim 15 recites “recieve” (line 5) which should be replaced with “receive”, to improve claim language.
Claim 17 recites “confgured” (line 6) which should be replaced with “configured”, to improve claim language.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5-7, 16, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2014/0346569 to Vielemeyer et al. (hereinafter Vielemeyer) (the reference US 2017/0062581 by You et al. (hereinafter You) and the reference US 2022/0020878 by Braun et al. (hereinafter Braun) are presented as evidence).
With respect to claim 1, Vielemeyer discloses a semiconductor device (e.g., integrated high electron mobility transistors (HEMTs), see the annotated Fig. 5 below) (Vielemeyer, Figs. 1-2, 5, ¶0004-¶0006, ¶0017, ¶0020-¶0026, ¶0030-¶0031), comprising:
a substrate (112) (Vielemeyer, Figs. 1-2, 5, ¶0021, ¶0026, ¶0030);
a heterojunction structure (116/118) (Vielemeyer, Figs. 1-2, 5, ¶0021) formed by a first group III-V compound layer (116, GaN) and a second group III-V compound layer (118, AlGaN) above the substrate (112);
a first gate electrode (106, the gate of the first HEMT transistor 102) (Vielemeyer, Fig. 5, ¶0020, ¶0030) deposited above the first group III-V compound layer (116) and the second group III-V compound layer (118), the first gate electrode (106) is electrically connected to a first gate terminal (e.g., wiring electrically connected to the gate 106 and to the control gate terminal g1 through the drain d1 of the HEMT transistors 202 to turn on the first HEMT 102) (Vielemeyer, Fig. 5, ¶0030-¶0031);
a second gate electrode (106’’, the gate of the second HEMT transistor 204) (Vielemeyer, Fig. 5, ¶0030-¶0031) deposited above the first group III-V compound layer (116) and the second group III-V compound layer (118), the second gate electrode (106’’) is electrically connected to a second gate terminal (e.g., the control gate terminal g2 of the second HEMT 204);
a source electrode (206, a common source shared by the first HEMT 102 and the second HEMT 204) (Vielemeyer, Fig. 5, ¶0031) deposited above the heterojunction structure (116/118), the source electrode (206) is electrically connected to a source terminal (e.g., conventionally, a source of a HEMT transistor is connected to a source terminal, such as a ground terminal in Fig. 7);
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a first drain electrode (110, the drain of the first HEMT 102) (Vielemeyer, Fig. 5, ¶0020, ¶0030) deposited above the heterojunction structure (116/118), the first drain electrode (110) is electrically connected to a drain terminal (e.g., conventionally, a drain of a FET transistor is connected to a drain terminal, as evidenced in Fig. 4 of Braun); and
a second drain electrode (110’’) (Vielemeyer, Fig. 5, ¶0030, ¶0031) deposited above the heterojunction structure (116/118), the second drain electrode (110’’) is electrically connected to the first gate terminal (106); wherein
the first gate electrode (106) (Vielemeyer, Fig. 5, ¶0030) is positioned between the source electrode (206) and the first drain electrode (110), and the second gate electrode (106’’) is positioned between the source electrode (206) and the second drain electrode (110’’).
Regarding claim 3, Vielemeyer discloses the semiconductor device of claim 1. Further, Vielemeyer discloses the semiconductor device, wherein the first group III-V compound layer (116) (Vielemeyer, Figs. 1-2, 5, ¶0021) comprises a GaN layer, and the second group III-V compound layer (118) comprises an AlGaN layer.
Regarding claim 5, Vielemeyer discloses the semiconductor device of claim 1. Further, Vielemeyer discloses the semiconductor device, wherein a distance between the second drain electrode (110’’) (Vielemeyer, Fig. 5, ¶0030-¶0031) and the second gate electrode (106’’) is less than a distance between the first drain electrode (110) and the first gate electrode (106).
Regarding claim 6, Vielemeyer discloses the semiconductor device of claim 1. Further, Vielemeyer discloses the semiconductor device, wherein a distance between the source electrode (206) and the second gate electrode (106’’) (Vielemeyer, Fig. 5, ¶0030-¶0031) is less than a distance between the source electrode (206) and the first gate electrode (106).
Regarding claim 7, Vielemeyer discloses the semiconductor device of claim 1. Further, Vielemeyer discloses the semiconductor device, further comprising: an AlN nucleation layer (114) (Vielemeyer, Figs. 1-2, 5, ¶0021) positioned between the substrate (e.g., growth substrate 112) and the heterojunction structure (116/118), to grow (e.g., conventionally heterojunction structure and transition layer 114 are formed on growth substrate 112 by epitaxial growth, as evidenced by You, ¶0009-¶0010) the first group III-V compound layer (116) and the second group III-V compound layer (118).
Note that limitations “to epitaxially grow” are directed towards the process of making an group III-V compound layers. It is well settled that "product-by-process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “to epitaxially grow” only requires a structure, group III-V compound layers, which does not distinguish the invention from Vielemeyer, who teaches the structure as claimed.
With respect to claim 16, Vielemeyer discloses a semiconductor device (e.g., integrated high electron mobility transistors (HEMTs), see the annotated Fig. 5 above) (Vielemeyer, Figs. 1-2, 5, ¶0004-¶0006, ¶0017, ¶0020-¶0026, ¶0030-¶0031), comprising:
a first die (e.g., gate driver HEMT 104 monolithically integrated with the power HEMT 102) (Vielemeyer, Figs. 1-2, 5, ¶0022-¶0023), having a substrate (112) (Vielemeyer, Figs. 1-2, 5, ¶0021), a heterojunction structure (116/118) (Vielemeyer, Figs. 1-2, 5, ¶0021) formed by two group III-V compound layers (116/118, GaN/AlGaN) on the substrate (112), a first field effect transistor (FET) device (e.g., the power HEMT 102) (Vielemeyer, Figs. 2, 5, ¶0022-¶0023) and a second FET device (e.g., the gate driver HEMT 104) formed on the substrate (112); wherein
the first FET device (102) (Vielemeyer, Figs. 2, 5, ¶0026, ¶0030-¶0031) having a source electrode (124/206, a common source shared by the first HEMT 102 and the second HEMT 104/204) and a first drain electrode (110) deposited above the heterojunction structure (116/118), and a first gate electrode (106, the gate of the first HEMT transistor 102) (Vielemeyer, Figs.2, 5, ¶0026, ¶0030) deposited above the two group III-V compound layers (116/118); and
the second FET device (104/204) (Vielemeyer, Figs. 2, 5, ¶0026, ¶0030) having the source electrode (124/206, a common source shared by the first HEMT 102 and the second HEMT 104/204) shared with the first FET device (102), a second drain electrode (110’/110’’) (Vielemeyer, Figs. 2, 5, ¶0026, ¶0030-¶0031) deposited above the heterojunction structure (116/118), and a second gate electrode (106’/106’’, the gate of the second HEMT transistor 104/204) (Vielemeyer, Figs. 2, 5) deposited above the two group III-V compound layers (116/118); and wherein
the second drain electrode (110’/110’’) (Vielemeyer, Figs. 2, 5, ¶0026, ¶0031) is electrically connected to the first gate electrode (106).
Regarding claim 18, Vielemeyer discloses the semiconductor device of claim 16. Further, Vielemeyer discloses the semiconductor device, further comprising: a first gate terminal (e.g., wiring electrically connected to the gate 106 and to the control gate terminal g1 through the drain d1 of the HEMT transistors 202 to turn on the first HEMT 102) (Vielemeyer, Fig. 5, ¶0030-¶0031) configured to receive a first driving signal (e.g., to turn on the first HEMT 102), the first gate electrode (106) and the second drain electrode (110’’) are electrically connected (e.g., through the drain d1 of the HEMT transistors 202) to the first gate terminal (g1); a second gate terminal (g2) configured to receive a second driving signal, the second gate electrode (106’’) is electrically connected to the second gate terminal (g2, to turn off the HEMT 102); a drain terminal, the first drain electrode (110) is electrically connected to the drain terminal (e.g., conventionally, a drain of a HEMT transistor is connected to a drain terminal); and a source terminal (e.g., conventionally, a source of a HEMT transistor is connected to a source terminal, such as ground in Fig. 7), the source electrode (206) is electrically connected to the source terminal.
Regarding claim 19, Vielemeyer discloses the semiconductor device of claim 18. Further, Vielemeyer discloses the semiconductor device, wherein: when turning on the first FET device (102) by the first driving signal (g1) and turning off the second FET device (204) by the second driving signal (g2), the drain terminal and the source terminal are conducted through the first FET device (102); and when turning off the first FET device by the first driving signal (g1) and turning on the second FET device by the second driving signal (g2), the first gate terminal and the source terminal are conducted through the second FET device (204).
Note that the recitation of claim 19 " when turning on the first FET device by the first driving signal and turning off the second FET device by the second driving signal, the drain terminal and the source terminal are conducted through the first FET device; and when turning off the first FET device by the first driving signal and turning on the second FET device by the second driving signal, the first gate terminal and the source terminal are conducted through the second FET device" are intended-use recitations. The Examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP §2114. In the instant case the above recitations of intended use do not distinguish the present invention over the prior art of Vielemeyer who teaches the structure as claimed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, 10, 14, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0020878 to Braun in view of Vielemeyer (US 2014/0346569).
With respect to claims 1 and 3, Braun discloses a semiconductor device (e.g., field effect transistors (FETs) including a power FET and a pull-down FET on the same die, see the annotated Figs. 3-4 below) (Braun, Figs. 2-4, ¶0004-¶0007, ¶0016-¶0025), comprising:
a substrate (201) (Braun, Figs. 2-4, ¶0018);
a structure (e.g., drift region 203/206 and body region 204/205) (Braun, Figs. 2-4, ¶0019) formed above the substrate (201);
a first gate electrode (e.g., the gate 210 or 222 in Fig. 4 of the power FET 22) (Braun, Figs. 2-4, ¶0020-¶0022) deposited above the structure (203 and 204/205), the first gate electrode (210/222) is electrically connected to a first gate terminal (Gate) (Braun, Fig. 4, ¶0022);
a second gate electrode (e.g., the gate 216 or 232 of the pull-down FET 23) (Braun, Figs. 2-4, ¶0020-¶0022) deposited above the structure (206 and 204/205), the second gate electrode (216/232) is electrically connected to a second gate terminal (GateB) (Braun, Fig. 4, ¶0022);
a source electrode (214 or 223/233 of the power FET 22 and the pull-down FET 23) (Braun, Figs. 2-4, ¶0020-¶0022) deposited above the structure (204/205), the source electrode (214 or 223/233) is electrically connected to a source terminal (Source) (Braun, Fig. 4, ¶0022);
a first drain electrode (208 or 221 of the power FET 22) (Braun, Figs. 2-4, ¶0020-¶0022) deposited above the structure, the first drain electrode (208 or
221) is electrically connected to a drain terminal (Drain) (Braun, Fig. 4, ¶0022); and
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a second drain electrode (218 or 231 in Fig. 4) (Braun, Figs. 2-4, ¶0020-¶0022) deposited above the structure, the second drain electrode (218 or 231) is electrically connected to the first gate terminal (Gate); wherein
the first gate electrode (210) (Braun, Fig. 3, ¶0020-¶0022) is positioned between the source electrode (214) and the first drain electrode (208), and the second gate electrode (216) is positioned between the source electrode (214) and the second drain electrode (218).
Further, Braun does not specifically disclose a heterojunction structure formed by a first group III-V compound layer and a second group III-V compound layer above the substrate; a first gate electrode deposited above the first group III-V compound layer and the second group III-V compound layer; a second gate electrode deposited above the first group III-V compound layer and the second group III-V compound layer; a source electrode deposited above the heterojunction structure; a first drain electrode deposited above the heterojunction structure (as claimed in claim 1); wherein the first group III-V compound layer comprises a GaN layer, and the second group III-V compound layer comprises an AlGaN layer (as claimed in claim 3).
However, Vielemeyer teaches forming a semiconductor device (e.g., see the annotated Fig. 5 above) (Vielemeyer, Figs. 1-2, 5, ¶0022-¶0023) comprising a gate driver HEMT (e.g., pull-down HEMT 104/204) monolithically integrated with the power HEMT (102) on the same die to remove a part from the driver die to remove parasitic resistance and capacitance between the dies to reduce voltage spikes at the gate of the power HEMT (Vielemeyer, ¶0004, ¶0038), as the gate driver HEMTs function as a gate voltage protection circuit. The power high-electron-mobility transistors (HEMTs) (Vielemeyer, ¶0003) provide significant power density, on-state resistance, switching frequency, and efficiency benefits over silicon MOSFETs in DC-DC converters. In Vielemeyer, a heterojunction structure (116/118) (Vielemeyer, Figs. 1-2, 5, ¶0021) is formed by a first group III-V compound layer (116, GaN) and a second group III-V compound layer (118, AlGaN) above the substrate (112), a first gate electrode (106, the gate of the first HEMT transistor 102) (Vielemeyer, Fig. 5, ¶0020, ¶0030) is deposited above the first group III-V compound layer (116) and the second group III-V compound layer (118), a second gate electrode (106’’, the gate of the second HEMT transistor 204) (Vielemeyer, Fig. 5, ¶0030-¶0031) is deposited above the first group III-V compound layer (116) and the second group III-V compound layer (118), a source electrode (206, a common source shared by the first HEMT 102 and the second HEMT 204) (Vielemeyer, Fig. 5, ¶0031) is deposited above the heterojunction structure (116/118), a first drain electrode (110, the drain of the first HEMT 102) (Vielemeyer, Fig. 5, ¶0020, ¶0030) is deposited above the heterojunction structure (116/118), and a second drain electrode (110’’) (Vielemeyer, Fig. 5, ¶0030, ¶0031) is deposited above the heterojunction structure (116/118), wherein the first group III-V compound layer (116) (Vielemeyer, Figs. 1-2, 5, ¶0021) comprises a GaN layer, and the second group III-V compound layer (118) comprises an AlGaN layer, to provide monolithically integrated a power HEMT with a gate driver HEMT that turn off the power HEMT to improve performance of the power HEMT.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Braun by integrating a power HEMT with a gate driver HEMT on the same die as taught by Vielemeyer to have the semiconductor device comprising: a heterojunction structure formed by a first group III-V compound layer and a second group III-V compound layer above the substrate; a first gate electrode deposited above the first group III-V compound layer and the second group III-V compound layer; a second gate electrode deposited above the first group III-V compound layer and the second group III-V compound layer; a source electrode deposited above the heterojunction structure; a first drain electrode deposited above the heterojunction structure (as claimed in claim 1); wherein the first group III-V compound layer comprises a GaN layer, and the second group III-V compound layer comprises an AlGaN layer (as claimed in claim 3), in order to provide monolithically integrated a power HEMT with a gate driver HEMT having improved power density, on-state resistance, switching frequency, and efficiency (Vielemeyer, ¶0003-¶0006, ¶0038).
Regarding claim 5, Braun in view of Vielemeyer discloses the semiconductor device of claim 1. Further, Braun discloses the semiconductor device, wherein a distance between the second drain electrode (218) (Braun, Fig. 3, ¶0020-¶0021) and the second gate electrode (216) is less than a distance between the first drain electrode (208) and the first gate electrode (210).
With respect to claim 10, Braun discloses a semiconductor device (e.g., field effect transistors (FETs) including a power FET and a pull-down FET on the same die, see the annotated Figs. 3-4 above) (Braun, Figs. 2-4, ¶0004-¶0007, ¶0016-¶0025), comprising:
a substrate (e.g., 201) (Braun, Fig. 3, ¶0018);
a layer (e.g., drift 203/206 layer and body 204/205 layer) (Braun, Fig. 3, ¶0020-¶0021) above the substrate (201);
a first gate electrode (210 or 221 in Fig. 4, the gate of the first FET transistor 22) (Braun, Figs. 3-4, ¶0020-¶0022) and a second gate electrode (216 or 232 in Fig. 4, the gate of the second FET transistor 23) deposited above the layer, wherein a length (Lg2) (Braun, Figs. 3-4, ¶0023) of the second gate electrode (216) is less than a length (Lg1) of the first gate electrode (210);
a source electrode (214 or 223/233 in Fig. 4, a common source shared by the first FET 22 and the second FET 23) (Braun, Figs. 3-4, ¶0021-¶0022), a first drain electrode (208 or 221 in Fig. 4, the drain of the first FET 22) (Braun, Figs. 3-4, ¶0020-¶0022) and a second drain electrode (218 or 231 in Fig. 4) deposited above the layer; wherein
the first gate electrode (210) (Braun, Fig. 3, ¶0021-¶0022) is positioned between the source electrode (214) and the first drain electrode (208), the second gate electrode (216 is positioned between the source electrode (214) and the second drain electrode (218), and the second drain electrode (218) is electrically connected to the first gate electrode (210).
Further, Braun does not specifically disclose a GaN layer epitaxially growing above the substrate; an AlGaN layer epitaxially growing above the GaN layer, to create a heterojunction structure; a first gate electrode and a second gate electrode deposited above the AlGaN layer; a source electrode, a first drain electrode and a second drain electrode deposited above the GaN layer.
However, Vielemeyer teaches forming a semiconductor device (e.g., see the annotated Fig. 5 above) (Vielemeyer, Figs. 1-2, 5, ¶0022-¶0023) comprising a gate driver HEMT (e.g., pull-down HEMT 104/204) monolithically integrated with the power HEMT (102) (Vielemeyer, Figs. 1-2, 5, ¶0022-¶0023) on the same die to remove a part from the driver die to remove parasitic resistance and capacitance between the dies to reduce voltage spikes at the gate of the power HEMT (Vielemeyer, ¶0004, ¶0038), as the gate driver HEMTs function as a gate voltage protection circuit. The power high-electron-mobility transistors (HEMTs) (Vielemeyer, ¶0003) provide significant power density, on-state resistance, switching frequency, and efficiency benefits over silicon MOSFETs in DC-DC converters. In Vielemeyer, a GaN layer (116) is grown above the growth substrate (112) (e.g., conventionally heterojunction structure and transition layer 114 are formed on growth substrate 112 by epitaxial growth, as evidenced by You, ¶0009-¶0010), an AlGaN layer (118) growing above the GaN layer (116), to create a heterojunction structure (116/118) (Vielemeyer, Figs. 1-2, 5, ¶0021), a first gate electrode (106, the gate of the first HEMT transistor 102) (Vielemeyer, Fig. 5, ¶0020, ¶0030) and a second gate electrode (106’’, the gate of the second HEMT transistor 204) deposited above the AlGaN layer (118); and a source electrode (206, a common source shared by the first HEMT 102 and the second HEMT 204) (Vielemeyer, Fig. 5, ¶0031), a first drain electrode (110, the drain of the first HEMT 102) (Vielemeyer, Fig. 5, ¶0020, ¶0030) and a second drain electrode (110’’) deposited above the GaN layer (116), to provide monolithically integrated a power HEMT with a gate driver HEMT that turn off the power HEMT to improve performance of the power HEMT.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Braun by integrating a power HEMT with a gate driver HEMT on the same die as taught by Vielemeyer to have the semiconductor device comprising: a GaN layer epitaxially growing above the substrate; an AlGaN layer epitaxially growing above the GaN layer, to create a heterojunction structure; a first gate electrode and a second gate electrode deposited above the AlGaN layer; a source electrode, a first drain electrode and a second drain electrode deposited above the GaN layer, in order to provide monolithically integrated a power HEMT with a gate driver HEMT having improved power density, on-state resistance, switching frequency, and efficiency (Vielemeyer, ¶0003-¶0006, ¶0038).
Regarding claim 14, Braun in view Vielemeyer discloses the semiconductor device of claim 10. Further, Braun discloses the semiconductor device, wherein at least one of the following relationships is satisfied: (1) a distance between the second drain electrode (218) (Braun, Fig. 3, ¶0021-¶0022) and the second gate electrode (216) is less than a distance between the first drain electrode (208) and the first gate electrode (210).
With respect to claim 16, Braun discloses a semiconductor device (e.g., field effect transistors (FETs) including a power FET and a pull-down FET on the same die, see the annotated Figs. 3-4 above) (Braun, Figs. 2-4, ¶0004-¶0007, ¶0016-¶0025), comprising:
a first die (e.g., the power FET and pull-down FET integrated on the same die) (Braun, Figs. 2-4, ¶0016), having a substrate (201) (Braun, Figs. 2-4, ¶0018), a structure (e.g., drift 203/206 layer and body 204/205 layer) (Braun, Fig. 3, ¶0020-¶0021) formed on the substrate (112), a first field effect transistor (FET) device (e.g., the power FET 22) (Braun, Figs. 2-4, ¶0020-¶0023) and a second FET device (e.g., pull-down FET 23) formed on the substrate (201); wherein
the first FET device (22) (Braun, Figs. 2-4, ¶0020-¶0023) having a source electrode (214 or 223 in Fig. 4) and a first drain electrode (208) deposited above the structure, and a first gate electrode (210 or 222 in Fig. 4, the gate of the first FET transistor 22) deposited above the structure; and
the second FET device (23) (Braun, Figs. 2-4, ¶0020-¶0023) having the source electrode (124 or 233 in Fig. 4) shared with the first FET device (22), a second drain electrode (218 or 231 in Fig. 4) deposited above the structure, and a second gate electrode (216 or 232 in Fig. 4, the gate of the second FET transistor 23) deposited above the structure; and wherein
the second drain electrode (218 or 231) (Braun, Figs. 2-4, ¶0020-¶0023) is electrically connected to the first gate electrode (210 or 222 in Fig. 4).
Further, Braun does not specifically disclose a heterojunction structure formed by two group III-V compound layers, wherein the first FET device having a source electrode and a first drain electrode deposited above the heterojunction structure, and a first gate electrode deposited above the two group III-V compound layers; and the second FET device having the source electrode shared with the first FET device, a second drain electrode deposited above the heterojunction structure, and a second gate electrode deposited above the two group III-V compound layers.
However, Vielemeyer teaches forming a semiconductor device (e.g., see the annotated Fig. 5 above) (Vielemeyer, Figs. 1-2, 5, ¶0022-¶0023) comprising a gate driver HEMT (e.g., pull-down HEMT 104/204) monolithically integrated with the power HEMT (102) (Vielemeyer, Figs. 1-2, 5, ¶0022-¶0023) on the same die to remove a part from the driver die to remove parasitic resistance and capacitance between the dies to reduce voltage spikes at the gate of the power HEMT (Vielemeyer, ¶0004, ¶0038), as the gate driver HEMTs function as a gate voltage protection circuit. The power high-electron-mobility transistors (HEMTs) (Vielemeyer, ¶0003) provide significant power density, on-state resistance, switching frequency, and efficiency benefits over silicon MOSFETs in DC-DC converters. In Vielemeyer, a GaN layer (116) is grown above the growth substrate (112) (e.g., conventionally heterojunction structure and transition layer 114 are formed on growth substrate 112 by epitaxial growth, as evidenced by You, ¶0009-¶0010), an AlGaN layer (118) growing above the GaN layer (116), to create a heterojunction structure (116/118) (Vielemeyer, Figs. 1-2, 5, ¶0021), a first gate electrode (106, the gate of the first HEMT transistor 102) (Vielemeyer, Fig. 5, ¶0020, ¶0030) and a second gate electrode (106’’, the gate of the second HEMT transistor 204) deposited above the AlGaN layer (118); and a source electrode (206, a common source shared by the first HEMT 102 and the second HEMT 204) (Vielemeyer, Fig. 5, ¶0031), a first drain electrode (110, the drain of the first HEMT 102) (Vielemeyer, Fig. 5, ¶0020, ¶0030) and a second drain electrode (110’’) deposited above the GaN layer (116), to provide monolithically integrated a power HEMT with a gate driver HEMT that turn off the power HEMT to improve performance of the power HEMT.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Braun by integrating a power HEMT with a gate driver HEMT on the same die as taught by Vielemeyer to have the semiconductor device comprising: a heterojunction structure formed by two group III-V compound layers, wherein the first FET device having a source electrode and a first drain electrode deposited above the heterojunction structure, and a first gate electrode deposited above the two group III-V compound layers; and the second FET device having the source electrode shared with the first FET device, a second drain electrode deposited above the heterojunction structure, and a second gate electrode deposited above the two group III-V compound layers, in order to provide monolithically integrated a power HEMT with a gate driver HEMT having improved power density, on-state resistance, switching frequency, and efficiency (Vielemeyer, ¶0003-¶0006, ¶0038).
Regarding claim 20, Braun in view Vielemeyer discloses the semiconductor device of claim 16. Further, Braun discloses the semiconductor device, wherein a layout size (Braun, Figs. 2-4, ¶0020-¶0023) of the second FET device (23) is less than a layout size of the first FET device (22).
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0020872 to De Vleeschouwer et al. (hereinafter De Vleeschouwer) in view of Vielemeyer (US 2014/0346569).
With respect to claim 1, De Vleeschouwer discloses a semiconductor device (e.g., high electron mobility transistor (HEMT)) (De Vleeschouwer, Figs. 3-4, ¶0003-¶0005, ¶0017, ¶0021-¶0032), comprising:
a substrate (85) (De Vleeschouwer, Figs. 3-4, ¶0021, ¶0025);
a heterojunction structure (86/87) (De Vleeschouwer, Figs. 3-4, ¶0025) formed by a first group III-V compound layer (86, GaN) and a second group III-V compound layer (87, AlGaN) above the substrate (85);
a first gate electrode (69) (De Vleeschouwer, Figs. 3-4, ¶0019, ¶0023, ¶0029) deposited above the first group III-V compound layer (86) and the second group III-V compound layer (87), the first gate electrode (69) is electrically connected to a first gate terminal (30);
a second gate electrode (70) (De Vleeschouwer, Figs. 3-4, ¶0019, ¶0023, ¶0029) deposited above the first group III-V compound layer (86) and the second group III-V compound layer (87), the second gate electrode (70) is electrically connected to a first gate terminal (30);
a source electrode (67) (De Vleeschouwer, Figs. 3-4, ¶0019, ¶0023, ¶0029) deposited above the heterojunction structure (86/87), the source electrode (67) is electrically connected to a source terminal (31);
a first drain electrode (65) (De Vleeschouwer, Figs. 3-4, ¶0019, ¶0023, ¶0029) deposited above the heterojunction structure (86/87), the first drain electrode (65) is electrically connected to a drain terminal (33); and
a second drain electrode (64) (De Vleeschouwer, Figs. 3-4, ¶0019, ¶0023, ¶0029) deposited above the heterojunction structure (86/87), the second drain electrode (64) is electrically connected to the drain terminal (33); wherein
the first gate electrode (69) (De Vleeschouwer, Figs. 3-4, ¶0023) is positioned between the source electrode (67) and the first drain electrode (65), and the second gate electrode (70) is positioned between the source electrode (67) and the second drain electrode (64).
Further, De Vleeschouwe does not specifically disclose that the second gate electrode is electrically connected to a second gate terminal; the second drain electrode is electrically connected to the first gate terminal.
However, Vielemeyer teaches forming a semiconductor device comprising a gate driver HEMT (104/204) monolithically integrated with the power HEMT (102) (Vielemeyer, Figs. 1-2, 5, ¶0022-¶0023) on the same die to remove a part from the driver die to remove parasitic resistance and capacitance between the dies to reduce voltage spikes at the gate of the power HEMT (Vielemeyer, ¶0004, ¶0038), as the gate driver HEMTs function as a gate voltage protection circuit. In Vielemeyer, a second gate electrode (106’’) is the gate of the second HEMT transistor (204) (Vielemeyer, Fig. 5, ¶0030-¶0031) that is electrically connected to a second gate terminal (e.g., the control gate terminal g2 of the second HEMT 204), and a second drain electrode (110’’) is the drain of the second HEMT transistor (204) that is electrically connected to the first gate terminal (106), to provide monolithically integrated a power HEMT with a gate driver HEMT that turn off the power HEMT to improve performance of the power HEMT.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of De Vleeschouwe by forming a gate driver HEMT monolithically integrated with the power HEMT on the same die as taught by Vielemeyer to have the semiconductor device, wherein the second gate electrode is electrically connected to a second gate terminal; the second drain electrode is electrically connected to the first gate terminal, in order to protect power HEMT by reducing voltage spikes at the gate of the power HEMT (Vielemeyer, ¶0004-¶0006, ¶0038).
Regarding claim 3, De Vleeschouwe in view Vielemeyer discloses the semiconductor device of claim 1. Further, De Vleeschouwe discloses the semiconductor device, wherein the first group III-V compound layer (86) (De Vleeschouwe, Figs. 3-4, ¶0025) comprises a GaN layer, and the second group III-V compound layer (87) comprises an AlGaN layer.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0346569to Vielemeyer in view of You et al. (US 2017/0062581, hereinafter You).
Regarding claim 2, Vielemeyer discloses the semiconductor device of claim 1. Further, Vielemeyer discloses the semiconductor device, wherein a two-dimension electron gas (2-DEG) region (Vielemeyer, Figs. 1-2, 5, ¶0018-¶0019, ¶0021) is formed at a transition between the first group III-V compound layer (116, GaN) and the second group III-V compound layer (118, AlGaN), but does not specifically disclose that the source electrode, the first drain electrode, and the second drain electrode are configured to make contact to the 2-DEG region to form ohmic contacts.
However, You teaches forming a semiconductor device (You, Fig. 12, ¶0010-¶0011, ¶0016-¶0019, ¶0029) comprising a two-dimension electron gas (2-DEG) region (116) formed by group III-V compound layers (112/114, GaN/AlGaN), and the source electrode (136) and the first and second drain electrodes (136) formed of ohmic metal to provide ohmic contacts to improve contact resistance between the source/drain electrodes and the channel layer, and thus to obtain improved GaN HEMT device having high breakdown voltage.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Vielemeyer by forming the source/drain electrodes made of ohmic metal as taught by You to have the semiconductor device, wherein the source electrode, the first drain electrode, and the second drain electrode are configured to make contact to the 2-DEG region to form ohmic contacts, in order to improve contact resistance between the source/drain electrodes and the channel layer, and thus to obtain improved GaN HEMT device having high breakdown voltage (You, ¶0001, ¶0010-¶0011, ¶0016-¶0019, ¶0029).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0346569to Vielemeyer in view of Inoue et al. (US 2005/0007200, hereinafter Inoue) and Ciou et al. (US 2020/0135869, hereinafter Ciou).
Regarding claim 4, Vielemeyer discloses the semiconductor device of claim 1. Further, Vielemeyer does not specifically disclose the semiconductor device, wherein a length of the second gate electrode is less than a length of the first gate electrode, and a length of the second drain electrode is less than a length of the first drain electrode.
However, Inoue teaches forming a semiconductor device (Inoue, Figs. 6, 9, ¶0002, ¶0008-¶0010, ¶0073) comprising a first FET including a first gate electrode (68) having a first length and a second FET including a second gate electrode (70) having a second length that is less than the first length (Inoue, Fig. 9, ¶0073), to increase a gain of the second transistor, and to provide an integrated circuit outputting high power and operating with high efficiency.
Further, Ciou teaches semiconductor device layouts (Ciou, Fig. 1B, ¶0014-¶0016, ¶0025-¶0032) with the source and drain contacts having different widths, wherein FETs formed on the same active region perform different functions and have different source/drain contact resistances. A source/drain contact resistance in a FET is proportional to the size of the source/drain contact. A source/drain contact with a larger footprint (e.g., with greater width/ length W2) (Ciou, Fig. 1B, ¶0032) provides a greater electrical contact area, thus reducing the contact resistance between the source/drain contact and a corresponding source/drain region. Reduced contact resistance at the source/drain regions of the FET facilitates current passing into/out of the FET through the source/drain contacts, which leads to an increase in switching speed for the FET. In Ciou, the source/drain contact resistance for different types of FETs on the same active region are tailored to maximize performance of the integrated circuit.
Thus, Ciou recognizes that the width/length of the source/drain contacts of FET transistors impacts contact resistance of FETs and performance of the integrated circuit. Thus, the width/length of the source/drain contacts of FET transistors is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the width/length of the source/drain contacts of FET transistors as Ciou has identified the width/length of the source/drain contacts of FET transistors as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a specific width/length of the source/drain contacts of FET transistors, such that a length of the second drain electrode is less than a length of the first drain electrode, in order to reduce switching losses as taught by Ciou (¶0014-¶0015, ¶0032) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Vielemeyer by forming a first gate electrode and a second gate electrode having different gate lengths as taught by Inoue, and optimizing width/length of the source/drain contacts of FET transistors as taught by Ciou to have the semiconductor device, wherein a length of the second gate electrode is less than a length of the first gate electrode, and a length of the second drain electrode is less than a length of the first drain electrode, in order to increase a gain of the second transistor, and to provide an integrated circuit outputting high power and operating with high efficiency; and to maximize performance of the integrated circuit (Inoue, ¶0002, ¶0008-¶0010, ¶0073; Ciou, ¶0014-¶0015, ¶0032).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0346569to Vielemeyer in view of Elbanhawy (US Patent No. 6,930,473).
Regarding claim 8, Vielemeyer discloses the semiconductor device of claim 1. Further, Vielemeyer discloses the semiconductor device, further comprising: a third gate electrode (106’, the gate of the second HEMT transistor 202) (Vielemeyer, Fig. 5, ¶0030-¶0031) deposited above the first group III-V compound layer (116) and the second group III-V compound layer (118); and a third drain electrode (110’) deposited above the heterojunction structure (116/118), the third drain electrode (110’) is electrically connected to the first gate terminal (106), but does not specifically disclose the semiconductor device, wherein the third gate electrode is electrically connected to a third gate terminal.
However, Elbanhawy teaches forming an integrated circuit (e.g., DC-DC converter) (Elbanhawy, Fig. 2a, Col. 1, lines 13-15; lines 61-67; Col. 2, lines 1-7; Col. 6, lines 20-48; Col. 7, lines 27-38) comprising a third FET transistor (Q3) and a controller (202) to provide respective gate voltage (VG3) to the third gate electrode of the third FET (Q3) that is electrically connected to a third gate terminal and third gate driver (D3), wherein the smaller third FET (Q3) is optimized to reduce switching losses and the larger FET (Q2) is optimized to reduce conduction loses.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Vielemeyer by forming an integrated circuit comprising a third FET transistor and a controller providing gate signals to the first to third FET transistor as taught by Elbanhawy to have the semiconductor device, the semiconductor device, wherein the third gate electrode is electrically connected to a third gate terminal, in order to provide improved integrated circuit with optimized FETs to reduce switching losses and conduction loses (Elbanhawy, Col. 1, lines 13-15; lines 61-67; Col. 2, lines 1-7; Col. 6, lines 40-48).
Regarding claim 9, Vielemeyer in view of Elbanhawy discloses the semiconductor device of claim 8. Further, Vielemeyer discloses the semiconductor device, wherein at least one of the following relationships is satisfied: (3) a distance between the second drain electrode (110’’) (Vielemeyer, Fig. 5, ¶0030-¶0031) and the second gate electrode (106’’) is less than a distance between the first drain electrode (110) and the first gate electrode (106), but does not specifically disclose that a distance between the third drain electrode and the third gate electrode is less than a distance between the second drain electrode and the second gate electrode.
However, Elbanhawy teaches optimizing smaller third FET (Q3) to reduce switching losses, and optimizing larger FET (Q2) to reduce conduction loses (Elbanhawy, Fig. 2a, Col. 6, lines 44-48). Thus, Elbanhawy recognizes that the size of the smaller FET transistor impacts switching losses of the device. Thus, the size of the smaller FET transistor is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the size of the smaller FET transistor as Elbanhawy has identified the size of the smaller FET transistor as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a specific size of the smaller FET transistor, such that distance between the third drain electrode and the third gate electrode is less than a distance between the second drain electrode and the second gate electrode, in order to reduce switching losses as taught by Elbanhawy (Col. 6, lines 44-48) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Vielemeyer/ Elbanhawy by optimizing a size of the third FET transistor as taught by Elbanhawy to have the semiconductor device, the semiconductor device, wherein a distance between the third drain electrode and the third gate electrode is less than a distance between the second drain electrode and the second gate electrode, in order to provide improved integrated circuit with optimized FETs to reduce switching losses and conduction loses (Elbanhawy, Col. 1, lines 13-15; lines 61-67; Col. 2, lines 1-7; Col. 6, lines 40-48).
Claims 10-12 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0346569to Vielemeyer in view of Inoue (US 2005/0007200) (the reference US 2017/0062581 by You is presented as evidence).
With respect to claim 10, Vielemeyer discloses a semiconductor device (e.g., integrated high electron mobility transistors (HEMTs), see the annotated Fig. 5 above) (Vielemeyer, Figs. 1-2, 5, ¶0004-¶0006, ¶0017, ¶0020-¶0026, ¶0030-¶0031), comprising:
a substrate (e.g., growth substrate 112) (Vielemeyer, Figs. 1-2, 5, ¶0021, ¶0026, ¶0030);
a GaN layer (116) growing above the substrate (112) (e.g., conventionally heterojunction structure and transition layer 114 are formed on growth substrate 112 by epitaxial growth, as evidenced by You, ¶0009-¶0010);
an AlGaN layer (118) growing above the GaN layer (116), to create a heterojunction structure (116/118) (Vielemeyer, Figs. 1-2, 5, ¶0021);
a first gate electrode (106, the gate of the first HEMT transistor 102) (Vielemeyer, Fig. 5, ¶0020, ¶0030) and a second gate electrode (106’’, the gate of the second HEMT transistor 204) deposited above the AlGaN layer (118);
a source electrode (206, a common source shared by the first HEMT 102 and the second HEMT 204) (Vielemeyer, Fig. 5, ¶0031), a first drain electrode (110, the drain of the first HEMT 102) (Vielemeyer, Fig. 5, ¶0020, ¶0030) and a second drain electrode (110’’) deposited above the GaN layer (116); wherein
the first gate electrode (106) (Vielemeyer, Fig. 5, ¶0030) is positioned between the source electrode (206) and the first drain electrode (110), the second gate electrode (106’’) is positioned between the source electrode (206) and the second drain electrode (110’’), and the second drain electrode (110’’) is electrically connected to the first gate electrode (106).
Note that limitations “epitaxially growing” are directed towards the process of making an group III-V compound layers. It is well settled that "product-by-process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “epitaxially growing” only requires a structure, group III-V compound layers, which does not distinguish the invention from Vielemeyer, who teaches the structure as claimed.
Further, Vielemeyer does not specifically disclose that a length of the second gate electrode is less than a length of the first gate electrode.
However, Inoue teaches forming a semiconductor device (Inoue, Figs. 6, 9, ¶0002, ¶0008-¶0010, ¶0073) comprising a first FET including a first gate electrode (68) having a first length and a second FET including a second gate electrode (70) having a second length that is less than the first length (Inoue, Fig. 9, ¶0073), to increase a gain of the second transistor, and to provide an integrated circuit outputting high power and operating with high efficiency.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Vielemeyer by forming a first gate electrode and a second gate electrode having different gate lengths as taught by Inoue to have the semiconductor device, wherein a length of the second gate electrode is less than a length of the first gate electrode, in order to increase a gain of the second transistor, and to provide an integrated circuit outputting high power and operating with high efficiency (Inoue, ¶0002, ¶0008-¶0010, ¶0073).
Regarding claim 11, Vielemeyer in view of Inoue discloses the semiconductor device of claim 10. Further, Vielemeyer discloses the semiconductor device, wherein a first FET (102) comprising the source electrode (206), the first drain electrode (110), and the first gate electrode (106) is controlled ON and OFF in response to a first driving signal applied to the first gate electrode (e.g., gate is connected to the drain of the driver transistor 202/204 to turn on/off the power HEMT 102) (Vielemeyer, Fig. 5, ¶0024, ¶0027, ¶0030-¶0031), and a second FET (204) comprising the source electrode (206), the second drain electrode (106’’), and the second gate electrode (106’’) is controlled ON and OFF in response to a second driving signal (g2) applied to the second gate electrode (106’’)
Regarding claim 12, Vielemeyer in view of Inoue discloses the semiconductor device of claim 10. Further, Vielemeyer discloses the semiconductor device, further comprising: a third drain electrode (110’, the drain of the transistor 202) deposited above the GaN layer (116), the third drain electrode (110’) is electrically connected to the first gate electrode (106); a third gate electrode (106’) deposited above the AlGaN layer (118), the third gate electrode (106’) is positioned between the source electrode (108’, note that the limitation “a source electrode” is interpreted as “one or more” because the claim uses an open ended transition phrase “comprising”, thus “the source electrode” is interpreted as including a common source 206 and a source 108’) and the third drain electrode (110’).
Regarding claim 14, Vielemeyer in view of Inoue discloses the semiconductor device of claim 10. Further, Vielemeyer discloses the semiconductor device, wherein at least one of the following relationships is satisfied: (1) a distance between the second drain electrode (110’’) (Vielemeyer, Fig. 5, ¶0030-¶0031) and the second gate electrode (106’’) is less than a distance between the first drain electrode (110) and the first gate electrode (106); and
(2) a distance between the source electrode (206) and the second gate electrode (106’’) (Vielemeyer, Fig. 5, ¶0030-¶0031) is less than a distance between the source electrode (206) and the first gate electrode (106).
Regarding claim 15, Vielemeyer in view of Inoue discloses the semiconductor device of claim 10. Further, Vielemeyer discloses the semiconductor device, further comprising: a source terminal (e.g., conventionally, a source of a HEMT transistor is connected to a source terminal, such as a ground terminal in Fig. 7) (Vielemeyer, Figs. 5, 7, ¶0030-¶0031), electrically connected to the source electrode (206); a drain terminal (e.g., conventionally, a drain of a HEMT transistor is connected to a drain terminal), electrically connected to the first drain electrode (110); a first gate terminal (e.g., wiring electrically connected to the gate 106 and to the control gate terminal g1 through the drain d1 of the HEMT transistors 202 to turn on the first HEMT 102) (Vielemeyer, Fig. 5, ¶0030-¶0031), electrically connected to the first gate electrode (106) and the second drain electrode (110’’), wherein the first gate terminal is configured to receive a first driving signal; and a second gate terminal, electrically connected to the second gate electrode, wherien the second gate terminal (g2) is configured to receive a second driving signal (e.g., to turn off the HEMT 102), and the semiconductor device is controlled by the first driving signal (g1) and the second driving signal (g2).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0346569to Vielemeyer in view of Inoue (US 2005/0007200) as applied to claim 12, and further in view of Elbanhawy (US Patent No. 6,930,473).
Regarding claim 13, Vielemeyer in view of Inoue discloses the semiconductor device of claim 12. Further, Vielemeyer discloses the semiconductor device, wherein at least one of the following relationships is satisfied: (3) a distance between the second drain electrode (110’’) (Vielemeyer, Fig. 5, ¶0030-¶0031) and the second gate electrode (106’’) is less than a distance between the first drain electrode (110) and the first gate electrode (106), but does not specifically disclose that a distance between the third drain electrode and the third gate electrode is less than a distance between the second drain electrode and the second gate electrode.
However, Elbanhawy teaches optimizing smaller third FET (Q3) to reduce switching losses, and optimizing larger FET (Q2) to reduce conduction loses (Elbanhawy, Fig. 2a, Col. 6, lines 44-48). Thus, Elbanhawy recognizes that the size of the smaller FET transistor impacts switching losses of the device. Thus, the size of the smaller FET transistor is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the size of the smaller FET transistor as Elbanhawy has identified the size of the smaller FET transistor as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a specific size of the smaller FET transistor, such that distance between the third drain electrode and the third gate electrode is less than a distance between the second drain electrode and the second gate electrode, in order to reduce switching losses as taught by Elbanhawy (Col. 6, lines 44-48) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Vielemeyer/Inoue by optimizing a size of the third FET transistor as taught by Elbanhawy to have the semiconductor device, wherein a distance between the third drain electrode and the third gate electrode is less than a distance between the second drain electrode and the second gate electrode, in order to provide improved integrated circuit with optimized FETs to reduce switching losses and conduction loses (Elbanhawy, Col. 1,lines 13-15;lines 61-67;Col. 2,lines 1-7;Col. 6, lines 40-48).
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0346569to Vielemeyer in view of Elbanhawy (US Patent No. 6,930,473).
Regarding claim 17, Vielemeyer discloses the semiconductor device of claim 16. Further, Vielemeyer discloses the semiconductor device, further comprising: a third FET device (202) (Vielemeyer, Fig. 5, ¶0030-¶0031), wherein the third FET device (202) is connected to the first FET device (102) to form a switching node (e.g., at the common drain d2/d3 connected to the first gate 106 of the first transistor 102), but does not specifically disclose the semiconductor device, further comprising: a second die co-packed with the first die in a chip, the second die having a third FET device and a control circuit; and wherein the control circuit is configured to provide a first driving signal to control the first FET device, a second driving signal to control the second FET device, and a third driving signal to control the third FET device.
However, Vielemeyer teaches forming a semiconductor device comprising a gate driver HEMT (104/204) monolithically integrated with the power HEMT (102) (Vielemeyer, Figs. 1-2, 5, ¶0022-¶0023) on the same die to remove a part from the driver die to remove parasitic resistance and capacitance between the dies to reduce voltage spikes at the gate of the power HEMT (Vielemeyer, ¶0004, ¶0038), as the gate driver HEMTs function as a gate voltage protection circuit.
Further, Elbanhawy teaches forming an integrated circuit (e.g., DC-DC converter) (Elbanhawy, Fig. 2a, Col. 1, lines 13-15; lines 61-67; Col. 2, lines 1-7; Col. 6, lines 20-48; Col. 7, lines 27-38) comprising a third FET transistor (Q3) and a controller (202) to provide respective gate voltage (VG3) to the third gate electrode of the third FET (Q3) that is electrically connected to a third gate terminal and third gate driver (D3), wherein the smaller third FET (Q3) is optimized to reduce switching losses and the larger FET (Q2) is optimized to reduce conduction loses. The control circuit (202) (Elbanhawy, Fig. 2a, Col. 6, lines 20-48) is configured to provide a first driving signal (VG1) to control the first FET device (Q1), a second driving signal (VG2) to control the second FET device (Q2), and a third driving signal (VG3) to control the third FET device (Q3), wherein the first FET and the second FET are formed on one integrated circuit and the third transistor (Q3) is formed in a second integrated circuit that is interconnected with the one integrated circuit to provide a DC-DC converter (Elbanhawy, Fig. 2a, Col. 7, lines 27-38).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Vielemeyer by forming two discrete integrated circuits interconnected to form a converter as taught by Elbanhawy, wherein the first die includes the first FET and the second FET, and wherein the second die includes a third FET transistor and a gate driver as taught by Vielemeyer to have the semiconductor device, further comprising: a second die co-packed with the first die in a chip, the second die having a third FET device and a control circuit; and wherein the control circuit is configured to provide a first driving signal to control the first FET device, a second driving signal to control the second FET device, and a third driving signal to control the third FET device, in order to provide improved integrated circuit with optimized FETs to reduce switching losses and conduction loses; and to protect power HEMT by reducing voltage spikes at the gate of the power HEMT by integrating the gate driver circuit with the FET device to remove parasitic resistance and capacitance (Elbanhawy, Col. 1, lines 13-15; lines 61-67; Col. 2, lines 1-7; Col. 6, lines 40-48; Vielemeyer, ¶0004-¶0006, ¶0038).
Regarding claim 20, Vielemeyer discloses the semiconductor device of claim 16. Further, Vielemeyer does not specifically disclose that a layout size of the second FET device is less than a layout size of the first FET device.
However, Elbanhawy teaches forming an integrated circuit (e.g., DC-DC converter) (Elbanhawy, Fig. 2a, Col. 1, lines 13-15; lines 61-67; Col. 2, lines 1-7; Col. 6, lines 20-48; Col. 7, lines 27-38) comprising smaller FETs (Q1 and Q3) enable reduction of switching losses, and the larger FETs (Q2 and Q4) optimized to reduce conduction loses.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Vielemeyer by forming an integrated circuit comprising smaller size FET transistors and larger size FET transistors with optimized sizes as taught by Elbanhawy to have the semiconductor device, wherein a layout size of the second FET device is less than a layout size of the first FET device, in order to provide improved integrated circuit with optimized FETs to reduce switching losses and conduction loses (Elbanhawy, Col. 1,lines 13-15;lines 61-67;Col. 2,lines 1-7; Col. 6,lines 40-48).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0346569to Vielemeyer in view of Braun (US 2022/0020878).
Regarding claim 20, Vielemeyer discloses the semiconductor device of claim 16. Further, Vielemeyer does not specifically disclose that a layout size of the second FET device is less than a layout size of the first FET device.
However, Braun teaches forming a power FET and a pull-down FET (Braun, Figs. 2-4, ¶0004-¶0007, ¶0016-¶0025) integrated together on a same die to mitigate negative impact caused by gate path noise of discrete FETs, wherein a layout size of the second FET device (e.g., pull-down FET 23) (Braun, Figs. 2-4, ¶0023) is less than a layout size of the first FET device (e.g., power FET 22).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Vielemeyer by forming an integrated circuit comprising a smaller size gate-control FET transistor and a larger size power FET transistor as taught by Braun to have the semiconductor device, wherein a layout size of the second FET device is less than a layout size of the first FET device, in order to provide improved integrated circuit with mitigated negative impact caused by gate path noise of discrete FETs (Braun, ¶0004-¶0007, ¶0016, ¶0023).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891