DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Andry et al. (20110205708) in view of Salmon (20210343690)
Regarding Claim 1, in Figs. 8-10, Andry et al. discloses a semiconductor device package comprising: a semiconductor device 308 having an active side and a backside opposite the active side; and a plurality of stacked and bonded layers 314/324 (layers 314/324 are stacked and bonded to laminate 3999), comprising: a first side (top or bottom) and a second side (top or bottom) (please note that there are two stacked and bonded layers 314/324, one is to the bottom of the device 308 and the other to the top of device 308, see Fig. 10 for example) opposite the first side, the first side having a base surface 327, a support feature 325 (pin fins/TSV)/316 (fluid cavity) that extends downwardly from the base surface, and sidewalls (sidewalls of microchannel (fluid cavity) 325 or TSVs 316 please see paragraphs 0020 and 0027) extend downwardly from the base surface and surround the base surface and the support feature 325/316; and a first interconnect 325 (pin fin/TSV) vertically disposed through the support feature 325/316, wherein the first interconnect is electrically coupled to the semiconductor device 308 through bonds 387 formed between the first side of the plurality of stacked and bonded layers 325/316 and the semiconductor device 308. Andry et al. fails to disclose the direct hybrid bonding between the active semiconductor device and the support structure (i.e. cool/cold plate). However, Salmon discloses a densely packed electronic systems where in Fig. 17, paragraph 173 and Fig. 18, paragraph 195, the required direct hybrid bonding is disclosed.
It would have been obvious to one of having ordinary skill before the effective filing date of the claimed invention to have the direct hybrid bonding in Adriy et al. as taught by Salmon in order to increase the density of the package (see paragraphs 0173 and 0195 of Salmon).
Regarding Claim 2, in Andriy et al., the plurality of stacked and bonded layers 314/324 collectively forms a cold plate (note the presence of (micro)channels (fluid) (cavities) 316 as containing coolant as cooling structure, and hence a cold plate)
Regarding Claim 3, in Andriy et al., the first side (top or bottom) of the cold plate 314/324 and the backside of the semiconductor device 308 define a coolant channel therebetween (note that coolant (fluid) cavities 316)
Regarding Claim 4, in Andriy et al., the semiconductor device 308 and the plurality of stacked and bonded layers 314/324 are part of an integrated cooling assembly.
Regarding Claim 5, and Andriy et al, one or more first layers (top or bottom) of the plurality of stacked and bonded layers 314/324 comprises the sidewalls and support feature 325/316; a second layer of the plurality of stacked and bonded layers is disposed between the base surface and the second side; the second layer comprises a second interconnect vertically disposed therethrough (see paragraphs 0019, 0020, 0033 and 0039); and the first and second interconnects (see paragraph 0019, 0020, 0033 and 0039) hare electrically coupled through bonds (see solder 389) formed between the one or more first layers and the second layer. Salmon discloses a densely packed electronic systems where in Fig. 17, paragraph 173 and Fig. 18, paragraph 195, the required direct hybrid bonding is disclosed.
Regarding Claim 6, in Andriy et al., the plurality of stacked and bonded layers 314/324 comprises a power plane and/or a ground plane.
Regarding Claim 7, in Andriy et al., the first interconnect connects the semiconductor device to at least one of the power plane or the ground plane (see paragraphs 0018, 0019, 0020, 0033, 0039)
Regarding Claim 8, in Andriy et al., the support feature 325/316 decreases in width from the base surface to a bonding interface of the first side of the plurality of stacked and bonded layers and the semiconductor device (see pin fin 316/325 in Fig. 5)
Regarding Claim 9, in Andriy et al, the sidewalls of plurality of stacked and bonded layers 314/324 are sloped (inherently so because of different shapes of pin/fins/TSV as shown in Fig. 5).
Regarding Claim 10, in Andriy et al, the plurality of stacked and bonded layers 314/324 comprises a stack of first layers; each of the first layers comprises a segment of the first interconnect (pin fins/TSV 325/316); and each segment of the first interconnect (pin fins/TSV 325/316) is connected to another vertically adjacent segment of the first interconnect through bonds formed between the first layers. Salmon discloses a densely packed electronic systems where in Fig. 17, paragraph 173 and Fig. 18, paragraph 195, the required direct hybrid bonding is disclosed.
Regarding Claim 11, in Figs 8-10, Andriy et al. discloses a microelectronic package comprising: a plurality of stacked and bonded layers 314/324 (layers 314/324 are stacked and bonded to laminate 3999) comprising: a first side and a second side opposite the first side, the first side having a base surface 327, sidewalls that surround the base surface and extend downwardly therefrom to define a cavity 316 (fluid cavity), and a support feature 325/316 disposed in the cavity (fluid is inside the fluid cavity 325 see paragraphs 0019, 0020, 0033 and 0039); and a first interconnect 325 vertically disposed through the support feature 325/316, wherein: the first interconnect is electrically coupled to a device 308 through bonds (through solder balls) formed between the first side and a backside of the device 308; and the first side of the plurality of stacked and bonded layers 314/324 and the backside of the device 308 define a coolant channel (fluid cavity 325) therebetween. Andry et al. fails to disclose the direct hybrid bonding between the active semiconductor device and the support structure (i.e. cool/cold plate). However, Salmon discloses a densely packed electronic systems where in Fig. 17, paragraph 173 and Fig. 18, paragraph 195, the required direct hybrid bonding is disclosed.
It would have been obvious to one of having ordinary skill before the effective filing date of the claimed invention to have the direct hybrid bonding in Adriy et al. as taught by Salmon in order to increase the density of the package (see paragraphs 0173 and 0195 of Salmon).
Regarding Claim 12, in Andriy et al, the plurality of stacked and bonded layers 314/324 collectively forms a cold plate (note the presence of (micro)channels (fluid) (cavities) 316 as containing coolant as cooling structure, and hence a cold plate)
Regarding Claim 13, in Andriy et al., wherein the device 308 and the plurality of stacked and bonded layers 314/324 are part of an integrated cooling assembly.
Regarding Claim 14, in Andriy et all, one or more first layers (top or bottom) of the plurality of stacked and bonded layers 314/324 comprises the sidewalls and support feature 325/316; a second layer of the plurality of stacked and bonded layers is disposed between the base surface and the second side; the second layer comprises a second interconnect vertically disposed therethrough (see paragraphs 0019, 0020, 0033 and 0039); and the first and second interconnects (see paragraph 0019, 0020, 0033 and 0039) hare electrically coupled through bonds (see solder 389) formed between the one or more first layers and the second layer. Salmon discloses a densely packed electronic systems where in Fig. 17, paragraph 173 and Fig. 18, paragraph 195, the required direct hybrid bonding is disclosed.
Regarding Claim 16, in Andriy et al., the device 308 is a first device and the first interconnect (fin pin/TSV 325 communicatively couples the first device and one or more second devices through the bonds (see paragraphs 0018, 0019, 0020, 0033, 0039). Salmon discloses a densely packed electronic systems where in Fig. 17, paragraph 173 and Fig. 18, paragraph 195, the required direct hybrid bonding is disclosed.
Regarding Claim 17, in Andriy et al., the one or more second devices 308 comprise a memory stack, and wherein the first device is a logic device.
Regarding Claim 18, in Andriy et al, the first side has a peripheral support feature disposed at a periphery of the first side, wherein the peripheral support feature comprises a plurality of interconnects vertically disposed therethrough, and wherein the plurality of interconnects communicatively couples the memory stack and the logic device (see paragraphs 0006, 0042 and 0043 in conjunction with paragraphs 0018, 0019, 0020, 0033, 0039)
Regarding Claim 19, in Andriy et al., the support feature (for example pin/fin/TSV) decreases in width from the base surface to a bonding interface of the first side of the plurality of stacked and bonded layers and the device (see the different shapes in Fig. 5).
Regarding Claim 20, in Andriy et al., the plurality of stacked and bonded layers 314/324 comprises a stack of first layers; each of the first layers comprises a segment of the first interconnect; and each segment of the first interconnect is connected to another vertically adjacent segment of the first interconnect through bonds (solders) formed between the first layers (see paragraphs 0006, 0042 and 0043 in conjunction with paragraphs 0018, 0019, 0020, 0033, 0039). Salmon discloses a densely packed electronic systems where in Fig. 17, paragraph 173 and Fig. 18, paragraph 195, the required direct hybrid bonding is disclosed.
Cited Art That is NOT Relied Upon
Theil (20250087560) (cited art that is NOT relied upon on this rejection) discloses cold plate with microchannels and interconnect structure in hybrid direct bonding scenario (see Figs. 1 and 13). Gao 20220302058, also NOT relied upon on this rejection, discloses hybrid direct bonding with TSVs and interconnects in connection to cavity/recess as shown in Figs. 13-16.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812
3/13/2026
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