Attorney Docket Number: 018166.0035
Filing Date: 11/17/2023
Claimed Foreign Priority Date: 3/08/2023 (KR10-2023-0030600)
Inventors: Yu et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the application filed 11/17/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA . In the event the determination of the status of the
application as to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis
(i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of
rejection if the prior art relied upon, and the rationale supporting the rejection, would be the
same under either status.
Claim Interpretation
Claims 4 and 10 recite the line “…ferroelectric material includes at least one of A1:HfO2, zirconium oxide and hafnium oxide (HfZrO), InSe, and CIPS…”, which will be interpreted as “…ferroelectric material includes at least one of HfO2, zirconium oxide and hafnium oxide (HfZrO), InSe, or CIPS…”.
Claim 8 recites the line “…wherein the semiconductor device is one of a memory device, a field effect transistor (FET), and an artificial synaptic device”, which will be interpreted as “…wherein the semiconductor device is one of a memory device, a field effect transistor (FET), or an artificial synaptic device”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sakai (US 20060017120 A1).
Regarding claim 9, Sakai (see, e.g., fig. 11) shows all aspects of the instant invention including a method of manufacturing a ferroelectric-based semiconductor device (e.g., device of fig. 1), the method comprising:
Preparing (see, e.g., paragraph 39 “…semiconductor substrate 1 is prepared first…”) a substrate (e.g., semiconductor substrate 1);
Depositing (see, e.g., paragraph 40 “…insulator buffer layer 2 is connected to one side of the semiconductor substrate 1…”) a gate oxide film (e.g., insulator buffer layer 2 + paragraph 50) on the substrate (e.g., semiconductor substrate 1);
Forming a channel (e.g., region 7) on the gate oxide film (e.g., insulator buffer layer 2 + paragraph 50);
Forming a source/drain (e.g., source region 5/drain region 6) on the channel (e.g., region 7); and
Plasma-treating (see, e.g., paragraph 92) the device (e.g., device of fig. 1);
Regarding claim 10, Sakai (see, e.g., fig. 11) shows wherein the substrate (e.g., semiconductor substrate 1) is a p-type silicon wafer (see, e.g., paragraph 39 “…the semiconductor substrate 1 may be silicon…” + paragraph 43), the gate oxide film (e.g., insulator buffer layer 2 + paragraph 50) includes a ferroelectric (see, e.g., paragraph 40 “…insulator buffer layer 2 is formed an oxide HfO2…”), and the ferroelectric material includes at least one of HfO2 (see, e.g., paragraph 40 “…insulator buffer layer 2 is formed an oxide HfO2…”), zirconium oxide and hafnium oxide (HfZrO), InSe, or CIPS.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Gros-Jean (US 20190386142 A1) in view of Inoue (US 20020054522 A1).
Regarding claim 1, Gros-Jean (see, e.g., fig. 1), shows most aspects of the instant invention including a ferroelectric-based semiconductor device (e.g., FeFET-type transistor of fig. 1) comprising:
A substrate (e.g., semiconductor substrate 101 + adjacent gate structure comprising gate layer 109 + ferroelectric layer 108) used as a gate (see, e.g., gate layer of adjacent gate structure);
A gate oxide film (e.g., gate insulator layer 107 + paragraph 33 “Gate insulator layer 107, is, for, example, made of a hafnium oxide”) formed on the substrate (e.g., semiconductor substrate 101 + adjacent gate structure comprising gate layer 109 + ferroelectric layer 108);
A channel (e.g., channel region 105) formed on the gate oxide film (e.g., gate insulator layer 107);
A source/drain (e.g., source and drain regions 102 and 103) formed on the channel (e.g., channel region 105);
Gros-Jean (see, e.g., fig. 1), however, fails to show wherein the semiconductor device is plasma-treated.
Inoue (see, e.g., fig. 3 + paragraph 86), in a similar device to Gros-Jean, teaches utilizing a plasma process in order to deposit a gate insulating film (see, e.g., paragraph 86 “…a gate insulating film 25 constituted by a silicon oxide film is formed on nearly the entire surface…by various kinds of film forming methods, such as the plasma CVD method”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the plasma-treatment of Inoue within the device of Gros-Jean, as plasma CVD was a well-known methodology in order to form gate insulating layers at the time of filing the invention, as taught by Inoue.
Regarding claim 2, Gros-Jean (see, e.g., fig. 1) shows wherein the substrate (e.g., semiconductor substrate 101 + adjacent gate structure comprising gate layer 109 + ferroelectric layer 108) is a p-type silicon wafer (see, e.g., fig. 1 + paragraph 31 “….semiconductor substrate…lightly P-type doped…Substrate 101 is, for example, made of silicon…”).
Regarding claim 3, Gros-Jean (see, e.g., fig. 1) shows wherein the gate oxide film (e.g., gate insulator layer 107) includes a ferroelectric material (see, e.g., paragraph 33 “Gate insulator layer 107, is, for, example, made of a hafnium oxide”).
Regarding claim 4, Gros-Jean (see, e.g., fig. 1) shows wherein the ferroelectric material (see, e.g., paragraph 33 “Gate insulator layer 107, is, for, example, made of a hafnium oxide”) includes at least one of HfO2 (see, e.g., paragraph 33), zirconium oxide and hafnium oxide (HfZrO), InSe, or CIPS.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Gros-Jean in view of Inoue further in view of Sharma (US 20200098926 A1).
Regarding claim 5, Gros-Jean in view of Inoue fails to teach wherein the channel is indium gallium zinc oxide (IGZO).
Sharma (see, e.g., fig. 1), in a similar device to Gros-Jean in view of Inoue, teaches a channel region (e.g., channel material 102) is indium gallium zinc oxide (IGZO) (see, e.g., paragraph 21 “…the channel material 102 may include indium gallium zinc oxide (IGZO)”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the IGZO of Sharma within the channel region of Gros-Jean in view of Inoue, as IGZO was a well-known material at the time of filing the invention to be used as a channel region material, as taught by Sharma, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Gros-Jean in view of Inoue further in view of Sharma and Ota (US 20020047170 A1).
Regarding claim 6, Gros-Jean in view of Inoue further in view of Sharma fails to teach a dielectric layer between the gate oxide film and the channel, wherein the dielectric layer includes HfO2.
Ota (see, e.g., fig. 16), in a similar device to Gros-Jean in view of Inoue further in view of Sharma, teaches a stack of oxide/dielectric layers (e.g., stacked gate insulating film 25, comprising HfSiO2 layer 23, HfO2 dielectric layer 22, et cetera) on a channel region (e.g., channel region between source/drain regions 9).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric HfO2 film of Ota under between the gate oxide and channel region of Gros-Jean in view of Inoue further in view of Sharma, in order to provide an increased dielectric thickness within the device, suppressing potential direct tunneling through the oxide layer (see, e.g., paragraph 106 of Ota).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Gros-Jean in view of Inoue further in view of Sharma, Ota, and Nishida (US 20210057455 A1).
Regarding claim 7, Gros-Jean in view of Inoue further in view of Sharma and Ota fails to teach wherein the semiconductor device is oxygen plasma-treated at radio frequency (RF) power of 300 W.
Nishida (see, e.g., fig. 2C), in a similar device to Gros-Jean in view of Inoue further in view of Sharma and Ota, teaches oxygen plasma-treatment on a layer of hafnium (e.g., hafnium monolayer) at radio frequency power of 300 W (see, e.g., paragraph 20 “the excess hafnium precursor is purged leaving a monolayer on the substrate as shown in FIG. 2B. Oxygen plasma is then applied in FIG. 2C (e.g., for 20 seconds with a RF power of 300 Watts) to oxidize the Hf monolayer and form hafnium oxide (HfO.sub.2) as shown in FIG. 2D”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the oxygen plasma-treatment process of Nishida to form one of the hafnium oxide layers present in Gros-Jean in view of Inoue further in view of Sharma and Ota, as oxygen-plasma treatment with a radio frequency power of 300 W on hafnium was well-known at the time of filing the invention as a method of forming hafnium oxide, as taught by Nishida.
Regarding claim 8, Gros-Jean (see, e.g., fig. 1) shows wherein the semiconductor device (e.g., FeFET-type transistor of fig. 1) is one of a memory device, a field effect transistor (FET) (see, e.g., paragraphs 2, 21, or 30), or an artificial synaptic device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814