Attorney Docket Number: 018166.0035
Filing Date: 11/17/2023
Claimed Foreign Priority Date: 3/08/2023 (KR10-2023-0030600)
Inventors: Yu et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments filed 4/13/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA . In the event the determination of the status of the
application as to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis
(i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of
rejection if the prior art relied upon, and the rationale supporting the rejection, would be the
same under either status.
Acknowledgement
The Amendment filed on 4/13/2026, responding to the Office action mailed 1/12/2026,
has been entered. Applicant amended claims 1, 4, and 7-10. The present Office action is made with all the suggested amendments being fully considered.
Response to Amendment
Applicant’s amendments to the claims have overcome the respective claim rejections under 35 U.S.C. 102 and 35 U.S.C. 103, as previously formulated in the Non- Final Office action mailed on 1/12/2026. Accordingly, all previous claim rejections are hereby withdrawn. Accordingly, pending in this application are claims 1-10. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Objections
Claim 1 is objected to because of the following informalities: “…wherein the semiconductor device…”, is unclear, per the remainder of the claim. For the purposes of examination, “…wherein the semiconductor device…” will be construed to recite “…wherein the ferroelectric-based semiconductor device…” for clarity. Appropriate correction is required.
Claim 9 is objected to because of the following informalities: “…plasma-treating the semiconductor device…”, is unclear, per the remainder of the claim. For the purposes of examination, “…plasma-treating the semiconductor device…” will be construed to recite “…plasma-treating the ferroelectric-based semiconductor device…” for clarity. Appropriate correction is required.
Claim 10 is objected to because of the following informalities: “…plasma-treating the semiconductor device…”, is unclear, per the remainder of the claim. For the purposes of examination, “…plasma-treating the semiconductor device…” will be construed to recite “…plasma-treating the ferroelectric-based semiconductor device…” for clarity. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Sakai (US 20060017120 A1) in view of Bhosle (US 20220028693 A1).
Regarding claim 9, Sakai (see, e.g., fig. 11) shows most aspects of the instant invention including a method of manufacturing a ferroelectric-based semiconductor device (e.g., device of fig. 11), the method comprising:
Preparing (see, e.g., paragraph 39 “…semiconductor substrate 1 is prepared first…”) a substrate (e.g., semiconductor substrate 1);
Depositing (see, e.g., paragraph 40 “…insulator buffer layer 2 is connected to one side of the semiconductor substrate 1…”) a gate oxide film (e.g., insulator buffer layer 2 + paragraph 50) on the substrate (e.g., semiconductor substrate 1);
Forming a channel (e.g., region 7) on the gate oxide film (e.g., insulator buffer layer 2 + paragraph 50);
Forming a source/drain (e.g., source region 5/drain region 6) on the channel (e.g., region 7); and
Plasma-treating (see, e.g., paragraph 92) the ferroelectric-based device (e.g., device of fig. 11);
Sakai (see, e.g., fig. 11), however, fails to show plasma-treating the ferroelectric-based semiconductor device using oxygen plasma at a radio-frequency power configured to reduce interface trap density at an interface between the channel and the gate oxide film.
Bhosle (see, e.g., 1-6), in a similar device to Sakai, teaches using oxygen plasma (see, e.g., paragraphs 11 or 42 + paragraph 32 “…utilize the sacrificial capping layer during the passivation process…”, note the sacrificial capping layer is formed by oxygen (see, e.g., paragraph 30) during the capping and passivating process of paragraphs 28-42, hence oxygen is used in the larger plasma treatment process) at a radio-frequency power (e.g., RF power supply 121) configured to reduce interface trap density (see, e.g., paragraphs 4 or 42 “Gate oxide reliability is mainly related to the defects and trap states at the gate oxide interface and the performance can be enhanced by passivating these defects. For example, these defects can be passivated using species such as…”) at an interface between the channel (e.g., channel beneath gate oxide 521) and the gate oxide film (e.g., gate oxide 521).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the oxygen plasma treatment of Bhosle within the method of Sakai, in order to reduce the gate oxide interface defects within the device (see, e.g., paragraph 4 of Bhosle).
Regarding claim 10, Sakai (see, e.g., fig. 11) shows wherein the substrate (e.g., semiconductor substrate 1) is a p-type silicon wafer (see, e.g., paragraph 39 “…the semiconductor substrate 1 may be silicon…” + paragraph 43), wherein the gate oxide film (e.g., insulator buffer layer 2 + paragraph 50) includes a ferroelectric (see, e.g., paragraph 40 “…insulator buffer layer 2 is formed an oxide HfO2…”), and wherein the ferroelectric material includes at least one of HfO2 (see, e.g., paragraph 40 “…insulator buffer layer 2 is formed an oxide HfO2…”), zirconium oxide and hafnium oxide (HfZrO), InSe, or CIPS.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Gros-Jean (US 20190386142 A1) in view of Bhosle (US 20220028693 A1).
Regarding claim 1, Gros-Jean (see, e.g., fig. 1), shows most aspects of the instant invention including a ferroelectric-based semiconductor device (e.g., FeFET-type transistor of fig. 1) comprising:
A substrate (e.g., semiconductor substrate 101 + adjacent gate structure comprising gate layer 109 + ferroelectric layer 108) used as a gate (see, e.g., gate layer of adjacent gate structure);
A gate oxide film (e.g., gate insulator layer 107 + paragraph 33 “Gate insulator layer 107, is, for, example, made of a hafnium oxide”) formed on the substrate (e.g., semiconductor substrate 101 + adjacent gate structure comprising gate layer 109 + ferroelectric layer 108);
A channel (e.g., channel region 105) formed on the gate oxide film (e.g., gate insulator layer 107);
A source/drain (e.g., source and drain regions 102 and 103) formed on the channel (e.g., channel region 105);
Gros-Jean (see, e.g., fig. 1), however, fails to show wherein the ferroelectric-based semiconductor device is oxygen plasma-treated at a radio frequency power configured to reduce interface trap density at an interface between the channel and the gate oxide film.
Bhosle (see, e.g., 1-6), in a similar device to Gros-Jean, teaches oxygen plasma treating (see, e.g., paragraphs 11 or 42 + paragraph 32 “…utilize the sacrificial capping layer during the passivation process…”, note the sacrificial capping layer is formed by oxygen (see, e.g., paragraph 30) during the capping and passivating process of paragraphs 28-42, hence oxygen is used in the larger plasma treatment process) at a radio-frequency power (e.g., RF power supply 121) configured to reduce interface trap density (see, e.g., paragraphs 4 or 42 “Gate oxide reliability is mainly related to the defects and trap states at the gate oxide interface and the performance can be enhanced by passivating these defects. For example, these defects can be passivated using species such as…”) at an interface between the channel (e.g., channel beneath gate oxide 521) and the gate oxide film (e.g., gate oxide 521).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the oxygen plasma treatment of Bhosle within the device of Gros-Jean, in order to reduce the gate oxide interface defects within the device (see, e.g., paragraph 4 of Bhosle).
Regarding claim 2, Gros-Jean (see, e.g., fig. 1) shows wherein the substrate (e.g., semiconductor substrate 101 + adjacent gate structure comprising gate layer 109 + ferroelectric layer 108) is a p-type silicon wafer (see, e.g., fig. 1 + paragraph 31 “…semiconductor substrate…lightly P-type doped…Substrate 101 is, for example, made of silicon…”).
Regarding claim 3, Gros-Jean (see, e.g., fig. 1) shows wherein the gate oxide film (e.g., gate insulator layer 107) includes a ferroelectric material (see, e.g., paragraph 33 “Gate insulator layer 107, is, for, example, made of a hafnium oxide”).
Regarding claim 4, Gros-Jean (see, e.g., fig. 1) shows wherein the ferroelectric material (see, e.g., paragraph 33 “Gate insulator layer 107, is, for, example, made of a hafnium oxide”) includes at least one of HfO2 (see, e.g., paragraph 33), zirconium oxide and hafnium oxide (HfZrO), InSe, or CIPS.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Gros-Jean in view of Bhosle further in view of Sharma (US 20200098926 A1).
Regarding claim 5, Gros-Jean in view of Bhosle fails to teach wherein the channel is indium gallium zinc oxide (IGZO).
Sharma (see, e.g., fig. 1), in a similar device to Gros-Jean in view of Bhosle, teaches a channel region (e.g., channel material 102) is indium gallium zinc oxide (IGZO) (see, e.g., paragraph 21 “…the channel material 102 may include indium gallium zinc oxide (IGZO)”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the IGZO of Sharma within the channel region of Gros-Jean in view of Bhosle, as IGZO was a well-known material at the time of filing the invention to be used as a channel region material, as taught by Sharma, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Gros-Jean in view of Bhosle further in view of Sharma and Ota (US 20020047170 A1).
Regarding claim 6, Gros-Jean in view of Bhosle further in view of Sharma fails to teach a dielectric layer between the gate oxide film and the channel, wherein the dielectric layer includes HfO2.
Ota (see, e.g., fig. 16), in a similar device to Gros-Jean in view of Bhosle further in view of Sharma, teaches a stack of oxide/dielectric layers (e.g., stacked gate insulating film 25, comprising HfSiO2 layer 23, HfO2 dielectric layer 22, et cetera) on a channel region (e.g., channel region between source/drain regions 9).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric HfO2 film of Ota under between the gate oxide and channel region of Gros-Jean in view of Bhosle further in view of Sharma, in order to provide an increased dielectric thickness within the device, suppressing potential direct tunneling through the oxide layer (see, e.g., paragraph 106 of Ota).
Allowable Subject Matter
Claims 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7: Gros-Jean in view of Bhosle further in view of Sharma and Ota neither anticipates nor renders obvious wherein the oxygen plasma treatment comprises oxygen plasma applied at a radio-frequency (RF) power of 300 W. These features in combination with other
elements in the claim are neither disclosed nor suggested by the prior art of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM
(Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts
to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be
reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Prosecution Insights