DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in the COUNTRY OF KOREA on 09/20/2022.
Election/Restrictions
Applicant's election without traverse of “Invention Group I and Species Group A-1 and B1 (Claims 1-4 and 7-14)” and new Claims 21-28 in the reply filed on 04/06/2026, is acknowledged. Claims 5-6 and 15-20 are now cancelled as requested in the reply filed on 04/06/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being obvious over US 2021/0057372 A1; Oh et al.; 02/2021; (“372”) in view of US 6,978,073 B2; Yamamoto et al.; 12/2005; (“073”).
Regarding Claim 1. 372 teaches in Figs. 2 and 6 about a semiconductor module having a double-sided heat dissipation structure, comprising:
a first heat dissipation substrate (Fig. 2, item 111) and a second heat dissipation substrate (Fig. 2, item 121) arranged to face each other (Fig. 2, items 111 and 121 face each other);
between the first heat dissipation substrate and the second heat dissipation substrate an area for mounting semiconductor dies in a pattern (Fig. 6, two die items 100b and two die items 100a are mounted in a staggered row pattern on a plane between heat dissipation substrates 111 and 121),
a first metal wiring layer (item 113) of the first heat dissipation substrate (item 113 is on item 111).
372 does not teach about a semiconductor module having a double-sided heat dissipation structure, comprising:
a guide stack disposed between the first heat dissipation substrate and the second heat dissipation substrate, and having an opening area for mounting a semiconductor die in a pattern;
a semiconductor die mounted within the opening area,
wherein the guide stack is spaced apart from a first metal wiring layer of the first heat dissipation substrate.
073 teaches in Fig. 3 about a semiconductor device, comprising:
a guide stack (item 14) with openings (items 14a).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the guide stack with openings of 073 to arrange in a pattern for mounting any device including the semiconductor dies of 372 in order align the positioning of these devices as taught by 073 in Fig. 1.
Allowable Subject Matter
Claims 2-4,7-14 and 21-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
Prosecution Insights