DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 in the reply filed on April 23, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 3, 4, 5, 6, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (2023/0225111, hereafter Lee ‘111).
Regarding claim 1, Lee ‘111 discloses a semiconductor memory device comprising: a substrate (100, par. 0021); a base insulating film (120, par. 0021) on an upper surface of the substrate; a plurality of first conductive patterns (130, par. 0033) on the base insulating film and spaced apart from each other, wherein the plurality of first conductive patterns extend in a first direction; a spacer structure (140, par. 0021) on a side surface of each of the plurality of first conductive patterns; a barrier metal film (BC/150, par. 0066) on a side surface of the spacer structure, wherein the barrier metal film extends through the base insulating film to be electrically connected to the substrate; a filling metal film (LP, par. 0021) on the barrier metal film, wherein the filling metal film fills at least a portion of a space between adjacent ones of the plurality of first conductive patterns; and a capacitor structure (190, par. 0021) on the filling metal film, wherein the capacitor structure is electrically connected to the filling metal film (Fig. 3).
Regarding claim 2, Lee ‘111 discloses a semiconductor memory device further comprising a plurality of insulating fences (170, par. 0063) on the substrate (100) and spaced apart from each other, wherein the plurality of insulating fences extend in a second direction intersecting the first direction, wherein the barrier metal film (BC/150) is on a portion of the upper surface of the substrate between adjacent ones of the plurality of insulating fences, and wherein the filling metal film (LP) fills at least a portion of a space between the adjacent ones of the plurality of insulating fences (Fig. 6).
Regarding claim 3, Lee ‘111 discloses a semiconductor memory device wherein a side surface of each of the plurality of insulating fences (170) is in contact with the filling metal film (LP) (Fig. 6).
Regarding claim 4, Lee ‘111 discloses a semiconductor memory device further comprising a capping pattern (138/139, par. 0034) on an upper surface of each of the plurality of first conductive patterns (130), wherein the barrier metal film (BC/150) is on an upper surface of the capping pattern (Fig. 3).
Regarding claim 5, Lee ‘111 discloses a semiconductor memory device wherein an upper surface of the filling metal film (LP) is farther than the upper surface of the capping pattern (138/139) from the upper surface of the substrate (100) (Fig. 3).
Regarding claim 6, Lee ‘111 discloses a semiconductor memory device further comprising: a direct contact (DC, Fig. 3, par. 0021) extending through the base insulating film (120, Fig. 3) to electrically connect the substrate (100, Fig. 3) and a first conductive pattern (130, Fig. 3) among the plurality of first conductive patterns; and a plurality of second conductive patterns (160, Fig. 6, par. 0037-0039) in the substrate, wherein the plurality of second conductive patterns are spaced apart from each other, wherein the plurality of second conductive patterns extend in a second direction intersecting the first direction, wherein a second conductive pattern among the plurality of second conductive patterns extends across a portion of the substrate between the filling metal film and the direct contact (Fig. 6).
Regarding claim 10, Lee ‘111 discloses a semiconductor memory device wherein the barrier metal film (BC/150) includes a metal nitride (par. 0065, 0069).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘111 in view of Kim et al. (2022/0384449, hereafter Kim).
Regarding claim 7, Lee ‘111 fails to disclose a semiconductor memory device further comprising a base metal film between the substrate and the base insulating film, wherein the barrier metal film is in contact with the base metal film.
However, Kim teaches a semiconductor memory device further comprising a base metal film (332, par. 0038) between the substrate (301, par. 0033) and the base insulating film (337, par. 0038), wherein the barrier metal film (313, par. 0059) is in contact with the base metal film (Fig. 1B).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee ‘111 with Kim by providing a base metal film between the substrate and base insulating film such that the barrier metal film is in contact with it in order to provide structural adhesion, prevent atomic diffusion, and facilitate electrical shielding and thermal management.
Regarding claim 8, Lee ‘111 fails to disclose a semiconductor memory device further comprising: a base semiconductor film between the substrate and the base metal film, wherein the base semiconductor film includes a semiconductor material doped with impurities; and a base silicide film between the base semiconductor film and the base metal film, wherein the base silicide film includes a metal silicide material.
However, Kim teaches a semiconductor memory device further comprising: a base semiconductor film (DC) between the substrate (301) and the base metal film (332), wherein the base semiconductor film includes a semiconductor material doped with impurities (par. 0038-0039); and a base silicide film (309) between the base semiconductor film and the base metal film, wherein the base silicide film includes a metal silicide material (par. 0064) (Fig. 1B).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee ‘111 with Kim by providing a base semiconductor film and base silicide film between the base metal film and substrate in order to ensure low-resistance ohmic interface and provide a buffer to prevent metal diffusion into bulk substrate.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘111 in view of Lee et al. (2022/0115382, hereafter Lee ‘382).
Regarding claim 9, Lee ‘111 fails to disclose a semiconductor memory device wherein an upper portion of the substrate includes an impurity area doped with impurities, wherein the barrier metal film is in contact with the impurity area.
However, Lee ‘382 teaches a semiconductor memory device wherein an upper portion of the substrate (100, par. 0020) includes an impurity area (1a/1b) doped with impurities (par. 0024), wherein the barrier metal film (157/153, par. 0037) is in contact with the impurity area (Fig. 1B).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee ‘111 with Lee ‘382 by including an impurity area in an upper portion of the substrate such that the barrier metal film is in contact with it because localized doping provides active terminals and creates a low-resistance path for charge transport.
Conclusion
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/C.M.B./ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Patent Examiner, Art Unit 2817
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