DETAILED ACTION
This Action is responsive to the Restriction/Election Response filed on 06/30/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group II, drawn to a semiconductor structure, and Species 1, reading on, e.g., FIG. 5B, in the reply filed on 06/30/2026 is acknowledged and entered into the record.
Claims 1-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected Group 1, drawn to a method of forming a semiconductor structure, and Species 2 and Species 3, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi (US 2021/0104529).
Regarding claim 14, Choi (see, e.g., FIG. 20A-FIG. 22B) discloses a semiconductor structure, comprising:
a plurality of gate filling structures 120G1, 124-1, 122-1 extending along a first direction e.g., x-direction (Para 0028-Para 0030; see FIG. 22A);
a plurality of isolation structures 112 each between two adjacent gate filling structures 120G1, 124-1 of the plurality of gate filling structures 120G1, 124-1, 122-1, wherein the plurality of isolation structures 112 extend along the first direction e.g., x-direction (see FIG. 20A), and an arrangement direction e.g., y-direction (see FIG. 20A, FIG. 22A) of the plurality of isolation structures 112 and the plurality of gate filling structures 120G1, 124-1, 122-1 is a second direction e.g., y-direction (Para 0021; see FIG. 20A, FIG. 22A); and
a plurality of semiconductor pillars AC each between a corresponding isolation structure 112 and a corresponding gate filling structure 120G1, 124-1, 122-1, wherein the plurality of semiconductor pillars AC extend along a third direction e.g., z-direction (see FIG. 22A) that intersects a first reference plane e.g., plane along the x-axis and y-axis, and the first direction e.g., x-direction (see FIG. 20A, FIG. 22A) and the second direction e.g., y-direction (see FIG. 20A, FIG. 22A) are in the first reference plane e.g., plane along the x-axis and y-axis (see FIG. 20A, FIG. 22A), wherein a length of an isolation structure 112 along the first direction e.g., x-direction (see FIG. 20A, FIG. 22A) is smaller than a length of a gate filling structure 120G1, 124-1, 122-1 along the first direction e.g., x-direction (see FIG. 20A, FIG. 22A) (Para 0021, Para 0022).
Regarding claim 15, Choi (see, e.g., FIG. 20A-FIG. 22B) teaches the semiconductor structure of claim 14, wherein the first direction e.g., x-direction (see FIG. 20A, FIG. 22A) and the third direction e.g., z-direction (see FIG. 22A) are in a second reference plane e.g., plane along the x-axis and z-axis (see FIG. 20A, FIG. 22A), an orthographic projection of the isolation structure 112 on the second reference plane e.g., plane along the x-axis and z-axis (see FIG. 20A, FIG. 22A) is a first orthographic projection e.g., bottom side surface of 112 on e.g., plane along the x-axis and z-axis (see FIG. 20A), and an orthographic projection of the gate filling structure 120G1, 124-1, 122-1 on the second reference plane e.g., plane along the x-axis and z-axis (see FIG. 20A, FIG. 22A) is a second orthographic projection e.g., bottom side surface of 120G1, 124-1, 122-1 on e.g., plane along the x-axis and z-axis (see FIG. 22A), and wherein two ends of the first orthographic projection e.g., bottom side surface of 112 on e.g., plane along the x-axis and z-axis (see FIG. 20A) are between two ends of the second orthographic projection e.g., bottom side surface of 120G1, 124-1, 122-1 on e.g., plane along the x-axis and z-axis (see FIG. 22A) along the first direction e.g., x-direction (see FIG. 20A, FIG. 22A).
Regarding claim 16, Choi (see, e.g., FIG. 20A-FIG. 22B) teaches the semiconductor structure of claim 14, wherein the semiconductor structure 120G1, 124-1, 122-1, 112, AC has a core area e.g., area right of EX2 (see FIG. 1) and an edge area e.g., area between EX1 and EX2 (see FIG. 1), and wherein the gate filling structure 120G1, 124-1, 122-1 is in the core area e.g., area right of EX2 (see FIG. 1) and the edge area e.g., area between EX1 and EX2 (see FIG. 1), and the isolation structure 112 is in the core area e.g., area right of EX2 (see FIG. 1).
Regarding claim 17, Choi (see, e.g., FIG. 20A-FIG. 22B) teaches the semiconductor structure of claim 14, wherein distances between the isolation structure 112 and the two adjacent gate filling structures 120G1, 124-1, 122-1 are equal along the second direction e.g., y-direction (see FIG. 20A, FIG. 22A) (Para 0065, Para 0083; see also FIG. 1).
Regarding claim 18, Choi (see, e.g., FIG. 20A-FIG. 22B) teaches the semiconductor structure of claim 14, wherein a difference in distances between the isolation structure 112 and the two adjacent gate filling structures 120G1, 124-1, 122-1 along the second direction e.g., y-direction (see FIG. 20A, FIG. 22A) is no greater than 10 nm (Para 0065, Para 0083; see also FIG. 1).
Regarding claim 20, Choi (see, e.g., FIG. 20A-FIG. 22B) discloses a memory system, comprising:
a semiconductor structure 120G1, 124-1, 122-1, 112, AC comprising:
a plurality of gate filling structures 120G1, 124-1, 122-1 extending along a first direction e.g., x-direction (Para 0028-Para 0030; see FIG. 22A);
a plurality of isolation structures 112 each between two adjacent gate filling structures 120G1, 124-1, 122-1 of the plurality of gate filling structures 120G1, 124-1, 122-1, wherein the plurality of isolation structures 112 extend along the first direction e.g., x-direction (see FIG. 20A), and an arrangement direction e.g., y-direction (see FIG. 20A, FIG. 22A) of the plurality of isolation structures 112 and the plurality of gate filling structures 120G1, 124-1, 122-1 is a second direction e.g., y-direction (Para 0021; see FIG. 20A, FIG. 22A);
a plurality of semiconductor pillars AC each between a corresponding isolation structure 112 and a corresponding gate filling structure 120G1, 124-1, 122-1, wherein the plurality of semiconductor pillars AC extend along a third direction e.g., z-direction (see FIG. 22A) that intersects a first reference plane e.g., plane along the x-axis and y-axis, and the first direction e.g., x-direction (see FIG. 20A, FIG. 22A) and the second direction e.g., y-direction (see FIG. 20A, FIG. 22A) are in the first reference plane e.g., plane along the x-axis and y-axis (see FIG. 20A, FIG. 22A), wherein a length of an isolation structure 112 along the first direction e.g., x-direction (see FIG. 20A, FIG. 22A) is smaller than a length of a gate filling structure 120G1, 124-1, 122-1 along the first direction e.g., x-direction (see FIG. 20A, FIG. 22A) (Para 0021, Para 0022); and
a controller e.g., peripheral circuit transistors coupled to the semiconductor structure 120G1, 124-1, 122-1, 112, AC and configured to control e.g., reading and writing the DRAM device the semiconductor structure 120G1, 124-1, 122-1, 112, AC (Para 0019).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2021/0104529), in view of Liu (US 2023/0043347).
Regarding claim 19, Choi (see, e.g., FIG. 20A-FIG. 22B) teaches the semiconductor structure of claim 14, the gate structure 120G1, 124-1, 122-1 comprises a gate layer 120G1 and a gate insulation layer 122-1 that is between the gate layer 120G1 and the semiconductor pillar AC (Para ; and distances between the isolation structure 112 and the gate insulation layers 122-1 in the two adjacent gate filling structures 120G1, 124-1, 122-1 are equal along the second direction e.g., y-direction (see FIG. 20A, FIG. 22A) (Para 0029, Para 0030, Para 0065; see also FIG. 1).
Although Choi shows substantial features of the claimed invention, Choi fails to expressly teach wherein the gate filling structure comprises a stop structure and a gate structure that are stacked along the third direction, wherein the stop structure comprises a stop block and a first insulation layer that is between the stop block and the semiconductor pillar.
Liu (see, e.g., FIG. 3-FIG. 6), on the other hand, teaches wherein the gate filling structure 101, 201, 203 comprises a stop structure 101 (on side surface of 201), 201 and a gate structure 203 that are stacked along the third direction e.g., vertical direction, wherein the stop structure 101 (on side surface of 201), 201 comprises a stop block 201 and a first insulation layer 101 (on side surface of 201) that is between the stop block 201 and the semiconductor pillar e.g., 100 between word lines 200 for the purpose of reducing the electric field intensity of the overlapping region A of the projections of the word line and further mitigating the GIDL leakage phenomenon (Para 0025, Para 0037).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the stop structure as described by Liu to the device Choi for the purpose of reducing the electric field intensity of the overlapping region A of the projections of the word line and further mitigating the GIDL leakage phenomenon (Para 0025, Para 0037).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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