DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claim(s) 1-2, 7, 14, and 18 filed on 8/4/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 4-6, 8-13, 15-17, and 19-20 have been considered. New Claim(s) 21 has been considered based on its merits, and entered. Claim(s) 3 is canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 5-12, filed 05/15/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of FURUYAMA and KWON.
Regarding Independent Claim(s) 1. The Applicant argues (see Remarks, pages 6-8), WU as modified by MA fails to disclose or suggest the amended features to claim 1, now recites, “wherein the second semiconductor layer…hole injection layer, the second sublayer…the hole injection layer is disposed…and a doping concentration of the first sublayer…and a doping concentration of the hole injection layer…first sublayer; and wherein the transparent conductive layer…first sublayer around the second sublayer.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, FURUYAMA teaches a light emitting element comprising: a first layer, an asperity surface and a second layer that supplies holes to the light emitting layer, and wherein the glass member is in contact with an upper surface of the first layer and the asperity surface which are mentioned below. KWON further teaches a light emitting device with respect to the relationship between the doping concentrations of different layers such as first conductive type layer, second conductive type layer, and the active (hole injection) layer.
Regarding Claim(s) 2, 4-21. The dependent claims 2, and 4-21 follow similar arguments as claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art as mentioned above.
Regarding WU prior art. The Applicant argues (see Remarks, page 6) that WU merely mentioned without teaching of the multi-layer structure and it was not clear such multi-layer structure encompass the first sublayer, the second sublayer and the hole injection layer and their specific relationship between the doping concentrations, as claimed in claim 1 of the instant application. Therefore WU fails to disclose or suggest the amended features of claim 1 as mentioned above. The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of FURUYAMA and KWON as mentioned in the above paragraph.
Regarding MA prior art. The Applicant argues (see Remarks, pages 6-8) that MA fails to disclose or suggest the amended features to claim 1 as demonstrated above. The Applicant further argues that the element, 108 (P-GaP current spreading layer) has been identified and equated to multiple distinct structural features, such as the first sublayer and the hole injection layer of the instant application. The Examiner respectfully disagrees with the arguments for the fact based on the Figure 1, and the paragraph, [0039]. Figure 1 of MA art discloses separate layers, 108 as P-GaP current spreading layer as equated to hole-injection layer of claim 1, and 110 as patterned contact point as equated to the second sublayer of claim 1. After forming the said layers, 108, and 110 per the paragraph [0039] of MA art, “immerse the roughened sample in acetone…then use electron beam evaporation to deposit…109 on the roughened…extension layer 108 and contact point 110.” Based on this procedure of immersing as given in [0039], the layer 109 is formed surrounding the layers of 108 and 110, therefore, two additional layers are formed such as 109 – indium tin oxide transparent film as the top layer above 110, the transparent layer of the same 109 covering the 108 and 110. Though the Figure 1 of MA art does not explicitly show the physical structure of the first sublayer as claimed in the instant application, the paragraph [0039] of the MA art confirms the co-existence of the first sublayer by forming the transparent indium tin oxide layer not only on top of the patterned contact point, 110, but also underneath and/or between the current spreading layer, 108 and the patterned contact point (please see the annotated Figure 1 of MA art). Therefore, the Examiner confirms that the first sublayer and the hole injection layer as claimed in the instant application are still read through the MA art with the supportive evidences as mentioned above.
Regarding Claim(s) 14. The Applicant argues (see Remarks, page 9) that WU as modified by MA fails to teach the amended feature, now recites, “wherein the second sublayer comprises…the net structure comprises a plurality of strip structures; and a part…second direction are not parallel.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of CHEN. For instance, CHEN prior art teaches the light-emitting device comprises a patterned sacrificial layer is arranged on the first type semiconductor layer both in horizontal and vertical directions to form a net structure (or strip structure).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8, 10-11, and 13, 15-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhiwei Wu et al, (hereinafter WU), CN 115394887 A in view of Hideto Furuyama, (hereinafter FURUYAMA), US 20160104824 A1, Oh Min Kwon et al, (hereinafter KWON), US 20140306178 A1, and Xiangzhu Ma et al, (hereinafter MA), CN 104576863 A.
Regarding Claim 1, WU teaches a light-emitting diode (LED) chip (Fig. 1, light-emitting element, [0038]), comprising:
a semiconductor laminated layer (Fig. 11, 20, an epitaxial stack, [0053]) comprising a first semiconductor layer (Fig. 11, 21, [0053]), a light-emitting layer (Fig. 11, 22, active layer, [0053]), and a second semiconductor layer (Fig. 11, 23, [0053]) arranged sequentially from bottom to top;
a transparent conductive layer (annotated Figure 11, first bonding layer is a transparent conductive layer, [0042]) disposed on the semiconductor laminated layer (Fig. 11, 20, an epitaxial stack, [0053]);
a transparent bonding layer (Fig. 11, 30, [0042]) disposed on the transparent conductive layer (annotated Figure 11, first bonding layer is a transparent conductive layer, [0042]); and
a transparent substrate (Fig. 11, 10, [0039]) disposed on the transparent bonding layer (Fig. 11, 30, [0042]);
wherein the second semiconductor layer comprises a first sublayer and a second sublayer (annotated Figure 11, the second semiconductor layer, 23, may also be a single layer or multi-layer structure, [0056]).
Though WU teaches the multi-layer structure of the second semiconductor layer, WU does not explicitly disclose a light-emitting diode (LED) chip comprising: wherein the second semiconductor layer comprises a first sublayer, a second sublayer and a hole injection layer, the second sublayer is disposed on a part of an upper surface of the first sublayer, the hole injection layer is disposed on a side of the first sublayer facing away from the second sublayer; and a doping concentration of the first sublayer is lower than that of the second sublayer, and a doping concentration of the hole injection layer is lower than or equal to that of the first sublayer; and wherein the transparent conductive layer is in contact with an upper surface of the second sublayer and a part of the upper surface of the first sublayer around the second sublayer.
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FURUYAMA teaches a light-emitting diode (LED) chip (Fig. 2A, 3, light emitting element) comprising: wherein the second semiconductor layer (Fig. 2A, 15, semiconductor layer) comprises a first sublayer (Fig. 2A, 11, first layer), a second sublayer (Fig. 2A, 15a, asperity surface) and a hole injection layer (Fig. 2A, 12, second layer/p-type cladding layer, supplies holes to the light emitting layer, [0020]), the second sublayer (Fig. 2A, 15a, asperity surface) is disposed on a part of an upper surface (annotated Figure 2A) of the first sublayer (Fig. 2A, 11, first layer), the hole injection layer (Fig. 2A, 12, second layer/p-type cladding layer, supplies holes to the light emitting layer, [0020]) is disposed on a side of the first sublayer (Fig. 2A, 11, first layer) facing away from the second sublayer (Fig. 2A, 13, light emitting layer); and wherein the transparent conductive layer (Fig. 2A, 32, glass member) is in contact with an upper surface (annotated Figure 2A) of the second sublayer (Fig. 2A, 15a, asperity surface) and a part of the upper surface (annotated Figure 2A) of the first sublayer (Fig. 2A, 11, first layer) around the second sublayer (Fig. 2A, 15a, asperity surface).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified WU to incorporate the teachings of FURUYAMA, such that a light-emitting diode (LED) chip comprising: wherein the second semiconductor layer comprises a first sublayer, a second sublayer and a hole injection layer, the second sublayer is disposed on a part of an upper surface of the first sublayer, the hole injection layer is disposed on a side of the first sublayer facing away from the second sublayer; and wherein the transparent conductive layer is in contact with an upper surface of the second sublayer and a part of the upper surface of the first sublayer around the second sublayer, so that to countermeasures against heat while manufacturing a high-power semiconductor light emitting devices (FURUYAMA, [0003]).
WU as modified by FURUYAMA does not disclose a light-emitting diode (LED) chip comprising: a doping concentration of the first sublayer is lower than that of the second sublayer, and a doping concentration of the hole injection layer is lower than or equal to that of the first sublayer.
KWON teaches a light-emitting diode (LED) chip (Fig. 5, 100C, light emitting device) comprising: a doping concentration of the first sublayer (Fig. 5, 130, first conductive type semiconductor layer [0052]) is lower than that of the second sublayer (Fig. 5, 150, second conductive type semiconductor layer, [0051-0052]), and a doping concentration of the hole injection layer (Fig. 5, 140, active layer/N-type dopant concentration of the first conductive type semiconductor layer, hole injection, [0052]) is lower than or equal to that of the first sublayer (Fig. 5, 130, first conductive type semiconductor layer, [0052]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have WU as modified by FURUYAMA to incorporate the teachings of KWON, such that a light-emitting diode (LED) chip comprising: a doping concentration of the first sublayer is lower than that of the second sublayer, and a doping concentration of the hole injection layer is lower than or equal to that of the first sublayer, so that the hole injection efficiency and internal quantum efficiency of the light emitting device may be improved (KWON, [0052]).
Though KWON teaches a light-emitting diode (LED) chip comprising: a doping concentration in the active layer as considered hole injection layer, WU as modified by FURUYAMA and KWON does not disclose a light-emitting diode (LED) chip comprising: a doping concentration of the first sublayer is lower than that of the second sublayer, and a doping concentration of the hole injection layer is lower than or equal to that of the first sublayer.
MA teaches a light-emitting diode (LED) chip (Fig. 1, [0002]) comprising: a doping concentration of the first sublayer (annotated Figure 1, the doping concentration of magnesium close to the buffer layer, 107, is 7x10¹⁷ cm³, [0036]) is lower than that of the second sublayer (Fig. 1, 110, patterned contact points, [0038]; annotated Figure 1, the magnesium doping concentration away from the buffer layer, 107, is from 8x10¹⁷ cm³ to 1x10¹⁹ cm³, [0036])), and a doping concentration of the hole injection layer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]) is lower than or equal to that of the first sublayer (annotated Figure 1, the doping concentration of magnesium close to the buffer layer, 107, is 7x10¹⁷ cm³, [0036]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have WU as modified by FURUYAMA and KWON to incorporate the teachings of MA, such that a light-emitting diode (LED) chip comprising: a doping concentration of the first sublayer is lower than that of the second sublayer, and a doping concentration of the hole injection layer is lower than or equal to that of the first sublayer, so that it will lead to high brightness light emitting diodes and their manufacturing processes that can improve the light extraction efficiency of light-emitting diodes. (MA, [0008]).
Regarding Claim 2, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 1.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]),wherein a thickness of the second semiconductor layer (annotated Figure 1 above) is less than 7 micrometers (μm) (annotated Figure 1 (above), the thickness of the magnesium-doped P-GaP current spreading layer is 2000 nm (2 micrometers or (μm)) to 4000 nm (4 micrometers or (μm)), [0011]), and a thickness of the second sublayer (Fig. 1, 110, patterned contact points, [0038]) is less than 1 μm (Fig. 1, the patterned contact point, 110 with a height of 200 nm (0.2 micrometers or (μm)).
Regarding Claim 4, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 1.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein the second sublayer (Fig. 1, 110, patterned contact points, [0038]) and the first sublayer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]) are made of a same material, and the material is one selected from the group consisting of gallium phosphide (GaP), aluminum gallium indium phosphide (AlGaInP) and aluminum indium phosphide (AlInP) (Fig. 1, P-GaP current spreading layer, 108; spin-coat positive photoresist onto the P-GaP current spreading layer, 108, and create a circular pattern, [0037]).
Regarding Claim 5, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 4.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein the first sublayer comprises a first GaP layer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]) and the second sublayer comprises (Fig. 1, 110, patterned contact points, [0038]) a second GaP layer (Fig. 1, P-GaP current spreading layer, 108; spin-coat positive photoresist onto the P-GaP current spreading layer, 108, and create a circular pattern or patterned contact points, 110, [0009], [0021], [0037-0038]).
Regarding Claim 6, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 5.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein a thickness of the first GaP layer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]) is in a range of 0.5 μm to 2 μm (annotated Figure 1 (above), the thickness of the magnesium-doped P-GaP current spreading layer is 2000 nm (2 micrometers or (μm)) to 4000 nm (4 micrometers or (μm)), [0011]), and a doping element of the first sublayer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]) is magnesium (Mg) (Fig. 1, magnesium-doped P-GaP current spreading layer, 108, [0011]).
Regarding Claim 7, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 1.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein a thickness of the first sublayer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]) is greater than (the magnesium-doped P-GaP current extension layer, 108 is preferably, 3000 nm thick, [0036] which is greater than the patterned contact point, 110 consists of multiple uniformly distributed cylinders, each with a diameter of 3 μm and a height of 200 nm) that of the second sublayer (Fig. 1, 110, patterned contact points, [0038]), the part of the upper surface of the first sublayer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]) around the second sublayer (Fig. 1, 110, patterned contact points, [0038]) is a roughened surface ([0037]), and a roughness of the roughened surface is in a range of 0.1 μm to 1 μm (annotated Figure 1, roughening depth of 200-400 nm (or 0.2 μm to 0.4 μm), [0037]); and the upper surface of the second sublayer (Fig. 1, 110, patterned contact points, [0038]) is flatter (annotated Figure 1) than that of the first sublayer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]).
FURUYAMA further teaches the LED chip (Fig. 2A, 3, light emitting element), wherein the transparent conductive layer (Fig. 2A, 32, glass member) is in contact with the roughened surface (Fig. 2A, 15a, asperity surface).
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Regarding Claim 8, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 1.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein a doping concentration of the first sublayer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]) is in a range of 1E17 atomic numbers per cubic meter (atoms/cm3) to 5E18 atoms/cm3 (the magnesium doped P-GaP current extension layer, the magnesium doping concentration near the buffer layer, 107, is 4x1017 cm3 to 8x1017 cm3 or preferably, 7x1017 cm3, [0012], [0036]).
Regarding Claim 10, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 1.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein the second sublayer (Fig. 1, 110, patterned contact points, [0038]) comprises a plurality of independent protrusion structures (annotated Figure 1) formed on the first sublayer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]).
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Regarding Claim 11, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 10.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein the plurality of protrusion structures are arranged in an array (annotated Figure 1), and a width of an upper surface of each protrusion structure (annotated Figure 1) is smaller than a distance between adjacent two of the plurality of protrusion structures (annotated Figure 1).
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Regarding Claim 13, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 10.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein a ratio of a sum of horizontal projection areas of upper surfaces of the plurality of protrusion structures (annotated Figure 1 and calculation therein, [0016]) to a horizontal projection area annotated Figure 1 and calculation therein, [0011]) of the first sublayer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]) is in a range of 5% to 30% (annotated Figure 1).
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Regarding Claim 15, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 14.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein a ratio of a horizontal projection area of an upper surface (annotated Figure 1 and calculation therein, [0016]) of the net structure (Fig. 1, graphic contact points, 110, [0038]; a type of patterning contact points, 110, [0020])) to a horizontal projection area (annotated Figure 1 and calculation therein, [0011]) of the first sublayer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]) is in a range of 5% to 30% (annotated Figure 1).
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Regarding Claim 16, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 1.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein the second sublayer (Fig. 1, 110, patterned contact points, [0038]) comprises a plurality of strip structures (Fig. 1, a type of patterning contact points, 110, [0020]) parallel to one another (annotated Figure 1), formed on the first sublayer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]).
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Regarding Claim 17, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 16.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein a ratio of a sum of horizontal projection areas (annotated Figure 1 and calculation therein, [0016]) of upper surfaces of the plurality of strip structures (Fig. 1, a type of patterning contact points, 110, [0020]) to a horizontal projection area (annotated Figure 1 and calculation therein, [0011]) of the first sublayer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]) is in a range of 5% to 30% (annotated Figure 1).
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Regarding Claim 18, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 1.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein a material of the hole injection layer (Fig. 1, current spreading layer, 108; the current first spreads laterally on the ITO layer and then is injected into the P-Gap current spreading layer, [0029]) is the same as that of the first sublayer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]), and the material of hole injection layer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]) is AlGaInP or AlInP (it should be noted that substituting (AlGaInP or AlInP) for (GaP) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143)").
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Regarding Claim 19, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 1.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein the LED chip (Fig. 1, light emitting diode, [0002]) further comprises a first electrode (Fig. 1, 112, second electrode, [0042]) and a second electrode (Fig. 1, 111, first electrode, [0040]), the first electrode (Fig. 1, 112, second electrode, [0042]) is in contact with the first semiconductor layer (Fig. 1, 101, GaAs substrate, [0042]), and the second electrode (Fig. 1, 111, first electrode, [0040]) is in contact with the transparent conductive layer (Fig. 1, 109, [0045]).
Regarding Claim 20, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 1.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), comprising a substrate (Fig. 1, 101, GaAs substrate, [0042]) and the LED chip (Fig. 1, light emitting diode, [0002]) disposed on the substrate (Fig. 1, 101, GaAs substrate, [0042]).
Regarding Claim 21, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 1.
FURUYAMA teaches the LED chip (Fig. 2A, 3, light emitting element), wherein a surface of the transparent conductive layer (Fig. 2A, 32, glass member) in contact with the first sublayer (Fig. 2A, 11, first layer) is a roughened surface, and another surface of the transparent conductive layer (Fig. 2A, 32, glass member) in in contact with the transparent bonding layer (Fig. 2A, 19, inorganic material layer) is also a roughened surface.
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Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over WU, in view of FURUYAMA, KWON, and MA as applied to claims 1-8, 10-11, and 13, 15-20 as above, and further in view of Yonghui Ge et al, (hereinafter GE), CN 109273569 A.
Regarding Claim 9, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 1.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein a doping concentration of the second sublayer (Fig. 1, 110, patterned contact points, [0038]) is at least 1E19 atoms/cm3 (annotated Figure 1 above, the magnesium doping concentration away from the buffer layer, 107, is from 8x1017 cm3 to 1x1019 cm3, [0036]).
WU as modified by FURUYAMA, KWON, and MA does not explicitly disclose the LED chip, wherein a doping element of the second sublayer is carbon (C).
GE teaches the LED chip (Fig. 1, light-emitting diode, [0031]), wherein a doping element of the second sublayer (Fig. 2, 42) is carbon (C) (Fig. 2, [0045-0047]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have WU as modified by WU as modified by FURUYAMA, KWON, and MA to incorporate the teachings of GE, such that the LED chip, wherein a doping element of the second sublayer is carbon (C), so that the high carbon doping concentration in the second sublayer prevents the second sublayer from having too weak a conductivity, which would affect hold injection into the active layer (GE, [0045]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over WU, in view of FURUYAMA, KWON, and MA as applied to claims 1-8, 10-11, and 13, 15-20 as above, and further in view of Hideo Nagai et al, (hereinafter NAGAI), JP 2005252222 A.
Regarding Claim 12, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 11.
MA further teaches the LED chip (Fig. 1, light emitting diode, [0002]), wherein the upper surface of each protrusion structure (annotated Figure 1) is parallel to the upper surface of the first sublayer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]), each protrusion structure (annotated Figure 1) further comprises a side wall (annotated Figure 1) connected between the upper surface of the protrusion structure (annotated Figure 1) and the upper surface of the first sublayer (Fig. 1, 108, magnesium-doped P-GaP current spreading layer, [0035]).
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WU as modified by FURUYAMA, KWON, and MA does not explicitly disclose the LED chip, wherein each protrusion structure further comprises a side wall, and the side wall is inclined relative to the upper surface of the protrusion structure at an inclination angle of 120-150 degrees (°).
NAGAI teaches the LED chip (Fig. 1a, LED chip 2, [0016]) wherein each protrusion structure (annotated Figure 21a) further comprises a side wall (annotated Figure 21a), and the side wall (annotated Figure 21a) is inclined relative to the upper surface of the protrusion structure (annotated Figure 21a) at an inclination angle of 120-150 degrees (°) (annotated Figure 21a).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have WU as modified by FURUYAMA, KWON, and MA to incorporate the teachings of NAGAI, such that the LED chip, wherein each protrusion structure further comprises a side wall, and the side wall is inclined relative to the upper surface of the protrusion structure at an inclination angle of 120-150 degrees (°), so that the concavo-convex structure thus improving the light extraction efficiency (NAGAI, [0011]).
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Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over WU, in view of FURUYAMA, KWON, and MA as applied to claims 1-8, 10-11, and 13, 15-20 as above, and further in view of Yi-Ming Chen et al, (hereinafter CHEN), US 20140319558 A1.
Regarding Claim 14, WU as modified by FURUYAMA, KWON, and MA teaches the LED chip as claimed in claim 1.
WU as modified by FURUYAMA, KWON, and MA teaches the LED chip, wherein the second sublayer comprises a net structure formed on the first sublayer, and the net structure comprises a plurality of strip structures; and a part of the plurality of strip structures is arranged on the first sublayer along a first direction, the other part of the plurality of strip structures is arranged on the first sublayer along a second direction, and the first direction and the second direction are not parallel.
CHEN prior art teaches the LED chip (Fig. 1, 100, light-emitting device) as claimed in claim 1, wherein the second sublayer (Fig. 5B, 151′″, patterned sacrificial layer, [0024]) comprises a net structure formed on the first sublayer (Figs. 5B/4H, 161 first-type semiconductor layer, [0024]) comprises, and the net structure ([0024]) comprises a plurality of strip structures (Fig. 5B, 151′″, patterned sacrificial layer, [0024]); and a part of the plurality of strip structures (Figs. 5B/4H, 161 first-type semiconductor layer, [0024]) is arranged on the first sublayer (Figs. 5B/4H, 161 first-type semiconductor layer, [0024]) along a first direction (annotated Figure 5B), the other part of the plurality of strip structures (annotated Figure 5B) is arranged on the first sublayer (Fig. 5B, 161 first-type semiconductor layer, [0024]) along a second direction (annotated Figure 5B), and the first direction (annotated Figure 5B) and the second direction are not parallel (annotated Figure 5B).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have WU as modified by FURUYAMA, KWON to incorporate the teachings of CHEN, such that a light-emitting diode (LED) chip, wherein the second sublayer comprises a net structure formed on the first sublayer, and the net structure comprises a plurality of strip structures; and a part of the plurality of strip structures is arranged on the first sublayer along a first direction, the other part of the plurality of strip structures is arranged on the first sublayer along a second direction, and the first direction and the second direction are not parallel. This arrangement would enable for easily designing the circuit layout thereon and for increasing heat dissipation efficiency and to further improve the lighting efficiency of the LED (CHEN, [0005-0006]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220231197 A1 – Figure 12
STATEMENT OF RELEVANCE – Schematic sectional view illustrating a flip-chip light emitting device shows the first and second bonding sub-layer with roughened surface.
US 20200220044 A1 – Figure 1
STATEMENT OF RELEVANCE – Schematic sectional view of a light emitting device wherein the bonding surfaces of the light emitting element and the first light transmissive layer are roughened surfaces.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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