DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species 1, Subspecies A in the reply filed on 4/9/2026 is acknowledged.
Claim Objections
Claims 1 and 11 are objected to because of the following informalities: the term “VETs” used in line 6 of claim 1 and line 8 of claim 11 should read as “VFETs”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8, 17, 21 and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 8 and 17 both recite the term “a second contact” twice, and later recite the phrase “the second contact”. It is unclear which of the two instances of “a second contact” is intended to be referred to by “the second contact”.
Due to their dependence on claim 8, claims 21 and 23 are also rejected on this basis.
Claim 21 includes the limitations “the second pad is a pad within a metal layer-to-poly layer, the third pad is a pad within a second metal layer-to-poly layer”. It is unclear to the examiner what the metes and bounds of the term “metal layer-to-poly layer” are, due to that term being mentioned only in passing in ¶ [0049] of the present application with no explanation of the term’s inherent properties being discussed. For the purposes of examination on the merits, it is assumed to imply that a metal material layer interfaces with a different material layer.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 7, 11-12, 16, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US patent publication US 20170309631 A1 (Cheng et al hereinafter Cheng).
Regarding claim 1, Cheng discloses a semiconductor structure (structure 100 of FIG. 13 ¶ [0021]), comprising: a first layer (FIG. 13, a lower layer including dielectric material 1002 and other lower layers ¶ [0050, 0056]) including a plurality of first power lines (FIG. 13, lower interconnects 1004, 1006, and non-shown lower supply rails VDD and ground rails GND are first power lines ¶ [0056]); a second layer (FIG. 13, a middle layer including portions 621, 622, 623, and transistor elements within them ¶ [0053]) including a plurality of vertical field effect transistors (VFETs) (FIG. 13, source/drain layers 106, 802, 804, fin structures 202, 204, and gate 614 form VFETs ¶ [0037, 0040, 0045, 0047]); a third layer (FIG. 13, an upper layer including dielectric material 1302 and other upper layers ¶ [0054, 0056]) including a plurality of second power line (FIG. 13, upper interconnects 1304, 1306, and non-shown upper supply rails VDD and ground rails GND are second power lines ¶ [0056]); wherein the second layer is disposed between the first layer and the third layer (FIG. 13, portions 621, 622, and 623 are between dielectric material layers 1002 and 1302), a first part of the VETs is connected to the first power lines (FIG. 13, source/drain layers 802, 804 of the VFETs connect to lower interconnects 1004, 1006 ¶ [0047]) and a second part of the VETs is connected to the second power lines (FIG. 13, source/drain layers 106 of the VFETs connect to upper interconnects 1304, 1306 ¶ [0037]).
Regarding claim 2, Cheng discloses the limitations of claim 1 as detailed above and further discloses that the first power lines and the second power lines extend along a first direction (lower interconnects 1004, 1006 and upper interconnects 1304, 1306 both extend in a width-direction that is horizontal relative to the cross-sectional view of FIG. 13).
Regarding claim 7, Cheng discloses the limitations of claim 1 as detailed above and further discloses that a first VFET (FIG. 13, the left VFET illustrated in the figure) of the VFETs has a drain and a source (FIG. 13, the left VFET includes source/drain regions 106 and 804 ¶ [0037, 0047]), and a plurality of channels (FIG. 13, fin structures 202 and 204 function as channels, and they are located in a layer that is between source/drains 106 and 804 along the z-axis ¶ [0040]) are between the drain and the source.
Regarding claim 11, Cheng discloses a semiconductor structure (structure 100 of FIG. 13 ¶ [0021]), comprising: a plurality of first conductive lines (FIG. 13, lower interconnects 1004, 1006, and non-shown lower supply rails VDD and ground rails GND are conductive lines ¶ [0056]) within a first layer (FIG. 13, a lower layer including dielectric material 1002 and other lower layers ¶ [0050, 0056]), wherein the first conductive lines include two first power lines (FIG. 13, lower interconnects 1004, 1006, and non-shown lower supply rails VDD and ground rails GND may function as first power lines ¶ [0056]); a plurality of vertical field effect transistors (VFETs) (FIG. 13, source/drain layers 106, 802, 804, fin structures 202, 204, and gate 614 form VFETs ¶ [0037, 0040, 0045, 0047]) within a second layer (FIG. 13, a middle layer including portions 621, 622, 623, and transistor elements within them ¶ [0053]); a plurality of second conductive lines (FIG. 13, upper interconnects 1304, 1306, and non-shown upper supply rails VDD and ground rails GND are conductive lines ¶ [0056]) within a third layer (FIG. 13, an upper layer including dielectric material 1302 and other upper layers ¶ [0054, 0056]), wherein the second conductive lines include two second power lines (FIG. 13, upper interconnects 1304, 1306, and non-shown upper supply rails VDD and ground rails GND may function as second power lines ¶ [0056]); wherein the second layer is disposed between the first layer and the third layer (FIG. 13, portions 621, 622, and 623 are between dielectric material layers 1002 and 1302), a first part of the VETs is connected to the first power lines (FIG. 13, source/drain layers 802, 804 of the VFETs connect to lower interconnects 1004, 1006 ¶ [0047]) and a second part of the VETs is connected to the second power lines (FIG. 13, source/drain layers 106 of the VFETs connect to upper interconnects 1304, 1306 ¶ [0037]).
Regarding claim 12, Cheng discloses the limitations of claim 11 as detailed above and further discloses that the first conductive lines and the second conductive lines extend along a first direction (lower interconnects 1004, 1006 and upper interconnects 1304, 1306 both extend in a width-direction that is horizontal relative to the cross-sectional view of FIG. 13).
Regarding claim 16, Cheng discloses the limitations of claim 11 as detailed above and further discloses that a first VFET (FIG. 13, the left VFET illustrated in the figure) of the VFETs has a drain and a source (FIG. 13, the left VFET includes source/drain regions 106 and 804 ¶ [0037, 0047]), and a plurality of channels (FIG. 13, fin structures 202 and 204 function as channels, and they are located in a layer that is between source/drains 106 and 804 along the z-axis ¶ [0040]) are between the drain and the source.
Regarding claim 18, Cheng discloses a semiconductor structure (structure 100 of FIG. 13 ¶ [0021]), comprising: a plurality of first power lines (non-shown supply rails VDD ¶ [0051, 0056]); a plurality of second power lines (non-shown supply rails VDD ¶ [0055-0056]); and a plurality of vertical field effect transistors (VFETs) (FIG. 13, source/drain layers 106, 802, 804, fin structures 202, 204, and gate 614 form VFETs ¶ [0037, 0040, 0045, 0047]) disposed between the first power lines and the second power lines (FIG. 13, the VFET elements are between interconnects 1004, 1006, 1304, and 1306 which connect to the non-shown power lines VDD ¶ [0051, 0055-0056]); wherein a first VFET of the VFETs connects to one of the first power lines or one of the second power lines (FIG. 13, the VFET structures connect to both sets of non-shown power lines VDD through interconnects 1004, 1006, 1304, and 1306 ¶ [0051, 0055-0056]).
Regarding claim 19, Cheng discloses the limitations of claim 18 as detailed above and further discloses that the first power lines and the second power lines extend along the same direction (non-shown power lines VDD all extend along length, width, and depth directions as a matter of structural necessity ¶ [0056]; while it is not explicitly stated that each power-line’s longest dimensions are aligned, it is sufficient that they each include dimensions along a direction, e.g. a width direction that corresponds to a horizontal direction based on the view of FIG. 13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publication US 20170309631 A1 (Cheng et al hereinafter Cheng) as applied to claim 2 above, and further in view of US 20200328212 A1 (Wu et al hereinafter Wu).
Regarding claim 3, Cheng discloses the limitations of claim 2 as detailed above but did not explicitly state that the third layer includes a plurality of first signal lines extend along the first direction. Cheng did mention that gates may include interconnects that extend upward (FIG. 13, interconnect 1308 ¶ [0051, 0055, 0056]).
Further, Wu discloses a semiconductor structure (the structure of FIGS. 2A-2C) wherein a third layer (FIG. 2C, the region along the z-axis including via contact 340 and power supply Vdd 310 ¶ [0046]) includes a first signal line (FIG. 2A, signal line 360 ¶ [0047]) that extend along a first direction (FIG. 2A, signal line 360 extends along a first length direction that is parallel to a length direction of signal line 350 which connects to a source contact 230, as well as width and height directions to varying degrees ¶ [0047, 0045]). A person of ordinary skill in the art before the effective filing date of the claimed invention would also recognize that the first signal line functions as a gate signal line through its connection to the gate (FIG. 2A, contact 344 connects signal line 360 to gate 120 ¶ [0047]), which provides a signal to the gate to allow it to control the transistor.
A person of ordinary skill in the art before the effective filing date of the claimed invention would also have found it obvious to duplicate the disclosed semiconductor structure in order to increase the functional capability of the device (see also MPEP 2144.04 VI. B). Having done so, the third layer includes a plurality of first signal lines extend along the first direction.
Cheng and Wu both pertain to the field of semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Cheng in view of Wu such that the third layer includes a plurality of first signal lines extend along the first direction, in order to form gate signal lines to provide signals to the gates and allow them to control the transistors.
Regarding claim 4, Cheng discloses the limitations of claim 2 as detailed above but did not explicitly disclose a fourth layer including a plurality of second signal lines. Cheng did mention that the gates may include interconnects that extend upward (¶ [0051]).
Further, Wu discloses a semiconductor structure (the structure of FIGS. 2A-2C) wherein a fourth layer (FIG. 2C, the region along the z-axis including via contact 340 and power supply Vdd 310 ¶ [0046]) includes a second signal line (FIG. 2A, signal line 360 ¶ [0047]). A person of ordinary skill in the art before the effective filing date of the claimed invention would also recognize that the second signal line functions as a gate signal line through its connection to the gate (FIG. 2A, contact 344 connects signal line 360 to gate 120 ¶ [0047]), which provides a signal to the gate to allow it to control the transistor.
A person of ordinary skill in the art before the effective filing date of the claimed invention would also have found it obvious to duplicate the disclosed semiconductor structure in order to increase the functional capability of the device (see also MPEP 2144.04 VI. B). Having done so, the fourth layer includes a plurality of second signal lines.
Cheng and Wu both pertain to the field of semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Cheng in view of Wu to include a fourth layer including a plurality of second signal lines, in order to provide gate signal lines to control a plurality of transistors.
Regarding claim 5, Cheng and Wu disclose the limitations of claim 4 as detailed above, and further disclose that the second signal lines extend along a second direction (Wu FIGS. 2A-2B, second signal lines 360 height-dimensions extend along a vertical Z height direction) and the first direction (the horizontal width direction of Cheng FIG. 13) is perpendicular to the second direction (the horizontal of Cheng is perpendicular to the vertical of Wu in the context of the combined device).
Claims 8, 10, 21, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claim 1 above, and further in view of an obvious modification to the device of Cheng.
Regarding claim 8, Cheng discloses the limitations of claim 1 as detailed above and further discloses that the second layer further includes a first contact (FIG. 13, a first seventh from the bottom of interconnect 1308 in the second layer region of the device ¶ [0055]), a first pad (FIG. 13, a second seventh from the bottom of interconnect 1308 in the second layer region of the device ¶ [0055]), a second contact (FIG. 13, a third seventh from the bottom of interconnect 1308 in the second layer region of the device ¶ [0055]), a second pad (FIG. 13, a fourth seventh from the bottom of interconnect 1308 in the second layer region of the device ¶ [0055]), a third pad (FIG. 13, a fifth seventh from the bottom of interconnect 1308 in the second layer region of the device ¶ [0055]), a fourth pad (FIG. 13, a sixth seventh from the bottom of interconnect 1308 in the second layer region of the device ¶ [0055]) and a second contact (FIG. 13, an uppermost seventh from the bottom of interconnect 1308 in the second layer region of the device ¶ [0055]) which are connected (FIG. 13, interconnect 1308’s constituent parts are connected to each other), and the second contact connects to a second signal line of the third layer (while not shown, Cheng teaches that ground or supply rails are coupled to interconnect 1308, which therefore connect to the second contact portion of interconnect 1308 ¶ [0055]). Cheng does not explicitly state that the first contact connects to a first signal line of the first layer.
However, Cheng does teach that a non-shown embodiment may include a via formed in dielectric 910 (FIG. 10), and that an interconnect may contact gate 614 through that non-shown via (¶ [0051]); such an interconnect would lead to the “first layer” portion of the device. Cheng also teaches that non-shown supply and ground rails may be formed on the interconnects that lead to the first layer portion of the device (¶ [0051]), and that forming signal lines at both top and bottom portions of the device avoid a connection between top and bottom contacts in any cell unit (¶ [0056]). Additionally, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to implement gate interconnects and signal lines at the first and third layers, in order to provide gate signal lines to control the gate of the transistor. Having done so, the first contact connects to a first signal line (the non-shown interconnect and ground rail that connect to gate 614 in the first layer portion of the device connect to the first seventh from the bottom of interconnect 1308 through gate 614 as it is depicted in FIG. 13) of the first layer.
Regarding claim 10, Cheng discloses the limitations of claim 1 as detailed above, but does not explicitly show that the second layer further includes a pad, and the pad connects a first pair of VFETs to a second pair of VFETs. While the view of FIG. 13 does not illustrate multiple pairs of VFETs, Cheng does however disclose a gate circuit embodiment (FIG. 14, gate circuit 1400) which includes several pairs of pFETs and nFETs that are configured in accordance with the structure of FIG. 13 (FIG. 14, pFETs 1406, 1408, 1410 and nFETs 1412, 1414, 1416 ¶ [0059]). The gate circuit of FIG. 14 also includes a connection between the drain terminal of pFET B 1408 and the source terminal of pFET C 1410 (FIG. 14, connection 1434), which is noted to be on the “bottom level” (B) of the circuit, the bottom level defined as any portion below layers based on the view of FIG. 13 (bottom level 1312 includes contact areas 902/904 ¶ [0056], which are considered part of the claimed “second layer” due to being above layer 1002 as discussed regarding claim 1).
While connection 1434 between nFET/pFET pair 1408/1414 and nFET/pFET pair 1410/1416 is not provided with a cross-sectional view, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to implement connection 1434 by means of a pad in the second layer (e.g. coplanar with contact areas 902/904), and that pad connects a first pair of VFETs (nFET/pFET B pair 1408/1414) to a second pair of VFETs (nFET/pFET C pair 1410/1416), in order to form a device including the gate circuit 1400.
Regarding claim 21, Cheng discloses the limitations of claim 8 as detailed above, and further discloses that the first pad is a bottom pad adjacent to the first layer (FIG. 13, the second seventh from the bottom of interconnect 1308 forming the first pad is the lowermost of the recited pads, and is therefore considered adjacent to the first layer), the second pad is a pad within a metal layer-to-poly layer (FIG. 13, the fourth seventh from the bottom of interconnect 1308 forming the second pad is formed at an interface of a metal material – metal interconnect 1308 – and another material – dielectric 622 ¶ [0055, 0045]; refer to rejection under 35 U.S.C. 112 section above for explanation on claim interpretation), the third pad is a pad within a second metal layer-to-poly layer (FIG. 13, the fifth seventh from the bottom of interconnect 1308 forming the third pad is formed at an interface of a metal material – metal interconnect 1308 – and another material – dielectric 622 ¶ [0055, 0045]; refer to rejection under 35 U.S.C. 112 section above for explanation on claim interpretation), and the fourth pad is a top pad adjacent to the third layer (FIG. 13, the sixth seventh from the bottom of interconnect 1308 forming the fourth pad is the uppermost of the recited pads, and is therefore considered adjacent to the third layer).
Regarding claim 23, Cheng discloses the limitations of claim 8 as detailed above, and further discloses that the first pad connects to a source terminal or a drain terminal of a first VFET of the VFETs (FIG. 13, the second seventh from the bottom of interconnect 1308 forming the first pad connects to source/drain 106 and contact areas 1202/1204 through dielectric 622; an electrical connection was not explicitly claimed), and the fourth pad connects to a source terminal or a drain terminal of the first VFET (FIG. 13, the sixth seventh from the bottom of interconnect 1308 forming the fourth pad connects to source/drain 106 and contact areas 1202/1204 through dielectric 622; an electrical connection was not explicitly claimed).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claim 12 above, and further in view of Wu.
Regarding claim 13, Cheng discloses the limitations of claim 12 as detailed above, but Cheng does not explicitly show a plurality of third conductive lines within a fourth layer. Cheng did mention that gates may include interconnects that extend upward (FIG. 13, interconnect 1308 ¶ [0051, 0055, 0056]).
Further, Wu discloses a semiconductor structure (the structure of FIGS. 2A-2C) wherein a fourth layer (FIG. 2C, the region along the z-axis including via contact 340 and power supply Vdd 310 ¶ [0046]) includes a third conductive line (FIG. 2A, signal line 360 ¶ [0047]). A person of ordinary skill in the art before the effective filing date of the claimed invention would also recognize that the third conductive line functions as a gate signal line through its connection to the gate (FIG. 2A, contact 344 connects signal line 360 to gate 120 ¶ [0047]), which provides a signal to the gate to allow it to control the transistor.
A person of ordinary skill in the art before the effective filing date of the claimed invention would also have found it obvious to duplicate the disclosed semiconductor structure in order to increase the functional capability of the device (see also MPEP 2144.04 VI. B). Having done so, the fourth layer includes a plurality of third conductive lines.
Cheng and Wu both pertain to the field of semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Cheng in view of Wu to include a plurality of third conductive lines within a fourth layer, in order to provide gate signal lines to control a plurality of transistors.
Regarding claim 14, Cheng and Wu disclose the limitations of claim 13 as detailed above, and further disclose that the third conductive lines extend along a second direction (Wu FIGS. 2A-2B, second signal lines 360 height-dimensions extend along a vertical Z height direction) and the first direction (the horizontal width direction of Cheng FIG. 13) is perpendicular to the second direction (the horizontal of Cheng is perpendicular to the vertical of Wu in the context of the combined device).
Claims 15 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Wu as applied to claim 14 above, and further in view of US patent publication US 20170033102 A1 (Kim et al hereinafter Kim).
Regarding claim 15, Cheng in view of Wu discloses the limitations of claim 14 as detailed above, but they do not further disclose that within one contacted poly pitch associated with the semiconductor structure, a ratio of a number of the second conductive lines to the one contacted poly pitch is greater than 2. A contacted poly pitch is understood as a separation distance between two gates.
However, Kim discloses a semiconductor structure (device 200 of FIGS. 5-8 ¶ [0017-0020]) wherein a third layer (FIGS. 6-7, insulating layer 205 and conductive lines within it constitute a third layer ¶ [0085]) includes a plurality of second conductive lines (FIGS. 5-7, conductive lines 260, 265, and 275 ¶ [0076, 0078, 0084]), and within one contacted poly pitch (FIGS. 5-7, a separation distance between gate electrodes 230 constitute a contacted poly pitch ¶ [0069]) associated with the semiconductor structure, a ratio of a number of the second conductive lines to the one contacted poly pitch is greater than 2 (FIGS. 5-7, conductive lines 260, 265, and 275 form 5 second conductive lines in the third layer of Kim in one contacted poly pitch ¶ [0076, 0078, 0084]). Kim also teaches that the distribution of the conductive lines among different layers affects both the management of space in the device as well as balances the possibility of interference between various conductive lines in the device (¶ [0089]), factors which a person of ordinary skill in the art before the effective filing date of the claimed invention would recognize as well-known result-effective variables to be adjusted for when manufacturing a semiconductor structure.
Cheng, Wu, and Kim all pertain to the field of semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Cheng in view of Wu further in view of Kim such that within one contacted poly pitch associated with the semiconductor structure, a ratio of a number of the second conductive lines to the one contacted poly pitch is greater than 2, as Kim has demonstrated such a configuration may be implemented to optimize for the use of space while avoiding interference being caused between the various conductive lines.
Regarding claim 22, Cheng in view of Wu and Kim disclose the limitations of claim 15 as detailed above, and they further disclose that the third conductive lines within the fourth layer (Cheng, non-illustrated supply or ground lines above interconnects 1308 of FIG. 13) extend along a second direction that is perpendicular to a first direction along which the second conductive lines within the third layer extend (as the supply or ground lines of Cheng extend in length, width, and height dimensions, the third conductive lines include an extension direction which is perpendicular to the first direction that the second conductive lines extend along), but they do not explicitly disclose that the fourth layer is disposed above the third layer, as the supply or ground lines of Cheng which connect to interconnects 1304, 1306, and 1308 are not illustrated in the figures.
However, Kim further discloses that third conductive lines (FIGS. 5-6, conductive lines 270 ¶ [0076]) are disposed within a fourth layer (FIGS. 6-7, the layer directly above insulating layer 205), and that fourth layer is disposed above the third layer (in the context of Kim, where the third layer is insulating layer 205 and conductive lines within it ¶ [0085]). Kim also demonstrated that their configuration of conductive lines disposed on layers separated along a vertical axis may be implemented to optimize for the use of space while avoiding interference being caused between the various conductive lines (¶ [0089]), as was discussed regarding claim 15. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Cheng in view of Wu and Kim further in view of Kim such that the fourth layer is disposed above the third layer, to implement the configuration of Kim in order to to optimize for the use of space while avoiding interference being caused between the various conductive lines.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claim 11 above, and further in view of an obvious modification to the device of Cheng.
Cheng discloses the limitations of claim 1 as detailed above and further discloses that the second layer further includes a first contact (FIG. 13, a first seventh from the bottom of interconnect 1308 in the second layer region of the device ¶ [0055]), a first pad (FIG. 13, a second seventh from the bottom of interconnect 1308 in the second layer region of the device ¶ [0055]), a second contact (FIG. 13, a third seventh from the bottom of interconnect 1308 in the second layer region of the device ¶ [0055]), a second pad (FIG. 13, a fourth seventh from the bottom of interconnect 1308 in the second layer region of the device ¶ [0055]), a third pad (FIG. 13, a fifth seventh from the bottom of interconnect 1308 in the second layer region of the device ¶ [0055]), a fourth pad (FIG. 13, a sixth seventh from the bottom of interconnect 1308 in the second layer region of the device ¶ [0055]) and a second contact (FIG. 13, an uppermost seventh from the bottom of interconnect 1308 in the second layer region of the device ¶ [0055]) which are connected (FIG. 13, interconnect 1308’s constituent parts are connected to each other), and the second contact connects to one of the second conductive lines (while not shown, Cheng teaches that ground or supply rails are coupled to interconnect 1308, which are therefore included among the second conductive lines and connect to the second contact portion of interconnect 1308 ¶ [0055]). Cheng does not explicitly state that the first contact connects to one of the first conductive lines.
However, Cheng does teach that a non-shown embodiment may include a via formed in dielectric 910 (FIG. 10), and that an interconnect may contact gate 614 through that non-shown via (¶ [0051]); such an interconnect would lead to a first conductive line in the “first layer” portion of the device. Cheng also teaches that non-shown supply and ground rails may be formed on the interconnects that lead to the first layer portion of the device (¶ [0051]), and that forming signal lines at both top and bottom portions of the device avoid a connection between top and bottom contacts in any cell unit (¶ [0056]). Additionally, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to implement gate interconnects and signal lines at the first and third layers, in order to provide gate signal lines to control the gate of the transistor. Having done so, the first contact connects to one of the first conductive lines (the non-shown interconnect and ground rail that connect to gate 614 in the first layer portion of the device connect to the first seventh from the bottom of interconnect 1308 through gate 614 as it is depicted in FIG. 13).
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent US 6252427 B1.
Conclusion
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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