DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The new title submitted 5/11/2026 is acknowledged and accepted by the Office.
Claim Rejections - 35 USC § 112
The rejection of Claim 10 under 35 U.S.C. 112(b), second paragraph is withdrawn. Claim 10 has been amended to overcome the rejection.
Claim Objections
The objection of Claims 18 and 19 is withdrawn. Claims 18 and 19 have been amended to overcome the objections.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, for:
A. In Claim 11 the: “wherein the resistance portion is in contact with the first trench portion at a front surface of the semiconductor substrate” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Allowable Subject Matter
Claims 3-5, 11, 16 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the
limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
A. Re claim 3, the prior art cannot be used to satisfy the limitation(s) of: wherein the resistance portion is provided to be in contact with the contact region, in combination with the additionally claimed features of claim 1.
B. Re claim 4, the prior art cannot be used to satisfy the limitation(s) of: wherein the resistance portion is provided to be in contact with (physically touching) the contact region, in combination with the additionally claimed features of claims 1-2.
C. Re claim 5, the prior art cannot be used to satisfy the limitation(s) of: wherein the resistance portion has a side wall provided to be in contact with the emitter region and a lower end provided to be in contact with the contact region, in combination with the additionally claimed features of claim 3.
D. Re claim 11, the prior art cannot be used to satisfy the limitation(s) of: the first trench portion is a dummy trench portion adapted to be set at an emitter potential; and wherein the resistance portion is in contact with the first trench portion at a front surface of the semiconductor substrate, in combination with the additionally claimed features of claim 1.
E. Re claim 16, the prior art cannot be used to satisfy the limitation(s) of: wherein the first trench portion includes a dummy gate trench portion set at a gate potential and being not in contact with the emitter region, in combination with the additionally claimed features of claim 1.
F. Re claim 19, the prior art cannot be used to satisfy the limitation(s) of: wherein the emitter region includes a second emitter region provided to be in contact with the first trench portion in the mesa portion, and the resistance portion is provided to be in contact with the second emitter region and spaced apart from the gate trench portion, and the contact region is further provided below the resistance portion, in combination with the additionally claimed features of claims 1, 17 and 18.
G. Re claim 20, the prior art cannot be used to satisfy the limitation(s) of: wherein the first emitter regions and the second emitter regions are alternately provided in a trench extending direction of the gate trench portion, in combination with the additionally claimed features of claims 1, 17, 18 and 19.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-8, 12, 15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Pfirsch et al (US 2013/0270632 A1-of record, hereafter Pfirsch) in view of Herbert et al (US 2009/0218620 A1-of record, hereafter Herbert).
Re claim 1, Pfirsch discloses in FIG. 1 a semiconductor device comprising:
a gate trench portion (102; [0027]) provided in a semiconductor substrate (103; [0027]);
a first trench portion (left 101; [0027]) provided in the semiconductor substrate (103) and adjacent to (beside) the gate trench portion (102);
an emitter region (left 112; [0028]) of a first conductivity type (n-type; [0028]) provided to be in contact with (physically touching) the gate trench portion (102) in a mesa portion (portion of 117 between 110 and 111) between the gate trench portion (102) and the first trench portion (left 101);
a contact region (left 115; [0028]) of a second conductivity type (p-type; [0028]) provided to be in contact with (physically touching) the first trench portion (left 101) in the mesa portion (portion of 117 between 110 and 111);
a metal layer (114; [0028] and [0033]) provided above the semiconductor substrate (103).
Pfirsch fails to disclose and a resistance portion of the first conductivity type provided in the semiconductor substrate (103) in contact with the metal layer (114) and the emitter region (left 112) and having a lower doping concentration than that of the emitter region (left 112).
However,
Herbert discloses in FIG. 8A a semiconductor device comprising a resistance portion (lightly doped N- diffused layer/N- Resistive Layer; [0026]) of the first conductivity type (n-type; [0026]) provided in a semiconductor substrate ([0011]) and in contact with an emitter region (N+ Source; [0026]) and having a lower doping concentration (N- vs N+; [0026]) than that of the emitter region (N+ Source).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Pfirsch by adding the resistance portion of Herbert, of the first conductivity type provided in a semiconductor substrate to be in contact with the metal layer and the emitter region (left 112) and having a lower doping concentration than that of the emitter region (left 112), providing improved reliability when the device is operated under high stress with high current, high current and high temperature (Herbert; [0028]).
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For the record, the inserted figure (annotated FIG. 1 of Pfirsch) depicts the resistance portion (lightly doped N- diffused layer/N- Resistive Layer) of Herbert provided in the semiconductor substrate (103), inserted between the metal layer (114) and the gate trench portion (102), and overlaying the emitter region (left 112).
Re claim 7, Pfirsch and Herbert disclose the semiconductor device according to claim 1, wherein the resistance portion (lightly doped N- diffused layer/N- Resistive Layer; see inserted figure above) is provided to be in contact with (physically touching) a contact hole (unlabeled opening in 105; [0027] and [0029]) provided between the metal layer (114) and a front surface (upper plane) of the semiconductor substrate (103), as part of the improved reliability of the device discussed for claim 1.
Re claim 8, Pfirsch and Herbert disclose the semiconductor device according to claim 1, wherein the contact region (left 115) is provided to extend beyond (see inserted figure above) a contact hole (unlabeled opening in 105; [0027] and [0029]) provided between the metal layer (114) and a front surface (upper plane) of the semiconductor substrate (103) from the first trench portion (left 101) in a trench arrangement direction (laterally left-to-right).
Re claim 12, Pfirsch and Herbert disclose the semiconductor device according to claim 1, semiconductor device according to claim 1, wherein the resistance portion (lightly doped N- diffused layer/N- Resistive Layer; see inserted figure above) is provided to be interposed between the emitter region (left 112) and the contact region (left 115) in a trench arrangement direction (laterally right-to-left).
Re claim 15, Pfirsch discloses the semiconductor device according to claim 1, wherein the first trench portion (left 101) is a dummy trench portion (no source structure; [0056]) set at an emitter potential (of 114; [0029]).
Re claim 17, Pfirsch discloses the semiconductor device according to claim 1, semiconductor device according to claim 1, wherein the first trench portion (left 101) is a gate trench portion (106 electrical gate coupling; [0028]) set at a gate potential (of 106; [0028] and [0030]).
Re claim 18, Pfirsch and Herbert disclose the semiconductor device according to claim 17, wherein the emitter region (left 112) includes a first emitter (left 112) region provided to be in contact with (physically touching) the gate trench portion (102) in the mesa portion (portion of 117 between 110 and 111), and the resistance portion (lightly doped N- diffused layer/N- Resistive Layer; see inserted figure above) is provided to be in contact with (physically touching) the first emitter region (left 112) and spaced apart (isolated) from the first trench portion (left 101), and the contact region (left 115) is provided below (under) the resistance portion (lightly doped N- diffused layer/N- Resistive Layer; see inserted figure above) provided to be in contact with (physically touching) the first emitter region (left 112) in the mesa portion (portion of 117 between 110 and 111), as part of the improved reliability of the device discussed for claim 1.
Claims 2, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Pfirsch and Herbert as applied to claim 1 above, and further in view of HATTA et al (US 2017/0229535 A1-of record, hereafter Hatta).
Re claim 2, Pfirsch and Herbert disclose the semiconductor device according to claim 1.
But, fail to disclose wherein a doping concentration of the resistance portion (N- Resistive layer) is equal to or greater than 5E17 cm⁻³ and equal to or smaller than 2E18 cm⁻³.
However,
Hatta discloses in FIG. 1 a semiconductor device comprising a doping concentration of a resistance portion (15b; [0061] and [0130]) is equal to or greater than 5E17 cm⁻³ and equal to or smaller than 2E18 cm⁻³ (1E17 cm⁻³ to 1E20 cm⁻³; [0130]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Pfirsch and Herbert by using Hatta’s resistance portion doping concentration of equal to or greater than 5E17 cm⁻³ and equal to or smaller than 2E18 cm⁻³ for the resistance portion of Herbert, increasing a voltage drop from a channel region to a source/emitter electrode while keeping an on-resistance low, thereby enhancing a short-circuit resistance (Hatta; [0010]).
Re claim 9, Pfirsch and Herbert disclose the semiconductor device according to claim 1.
But, fail to disclose wherein the contact region (left 115) is separated from the gate trench portion (102) by 0.1 µm or more in a trench arrangement direction (laterally left-to-right).
However,
Hatta discloses the resistance portion (15b) to have a width (LNO; [0079]) of (0.1 to 10 µm; [0079]). Therefore, the contact region (left 115) is separated from the gate trench portion (102) by the resistance portion by 0.1 µm or more in a trench arrangement direction (laterally left-to-right), as would be part of the device discussed for claim 2.
Re claim 10, Pfirsch and Herbert disclose the semiconductor device according to claim 1.
But, fail to disclose wherein the resistance portion (N- Resistive layer; see inserted figure above) includes a region having a doping concentration increasing from an end of the first trench portion (left 101) side toward an end of the gate trench portion (102) side in a trench arrangement direction (laterally left-to-right).
However,
Hatta discloses the resistance portion (15b) to have a retro-grade ([0091]) or a step-like profile ([0091]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use the retro-grade or the step-like profile of Hatta, such that the resistance portion includes a region having a doping concentration increasing from an end of the first trench portion (left 101) side toward an end of the gate trench portion (522) side in a trench arrangement direction (laterally left-to-right), to achieve the functionality of the device of claim 2.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Pfirsch and Herbert as applied to claim 1 above, and further in view of Hatta and SHIRAKAWA (US 2020/0203512 A1-of record, hereafter Shirakawa).
Re claim 1, Pfirsch and Herbert disclose the semiconductor device according to claim 1.
But, fail to disclose wherein a width of the resistance portion (N- Resistive layer; see inserted figure above) in a trench arrangement direction (laterally left-to-right) is 5 to 25% of a width of the mesa portion (portion of 117 between 110 and 111).
However,
A. Hatta discloses a width (LNO; [0079]) of a resistance portion (15b) to be 0.1 to 10 µm ([0079]).
And,
B. Shirakawa discloses a semiconductor device comprising mesa widths of 0.7 to 2 µm ([0006]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further modify the structure of Pfirsch and Herbert using the resistance portion width of Hatta for the devices discussed for claim 2; and using the mesa widths of Shirakawa to change the density of trenches to reduce device ON resistance (Shirakawa; [0074]).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Pfirsch and Herbert as applied to claim 1 above, and further in view of NAITO (US 2018/0374948 A1-of record, hereafter Naito).
Re claims 13-14, Pfirsch and Herbert disclose the semiconductor device according to claim 1.
But, fail to disclose the semiconductor device further comprising a contact trench portion in the mesa portion (portion of 117 between 110 and 111) provided to extend in a depth direction from a front surface (upper plane) of the semiconductor substrate (103); and wherein a lower end of the contact region (left 115) is deeper than a lower end of the contact trench portion.
However,
Naito discloses in FIGS. 1-2 a semiconductor device comprising a contact trench portion (27; [0067]) in a mesa portion (between adjacent trench portions; [0067]) provided to extend in a depth direction (downward) from a front surface (upper plane) of a semiconductor substrate (10; [0067]); and wherein a lower end (bottom) of a contact region (28; [0068]) is deeper than (below; [0068]) a lower end (bottom) of the contact trench portion (27).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further modify the structure of Pfirsch and Herbert by using the contact trench of Naito, in the mesa portion (portion of 117 between 110 and 111) provided to extend in a depth direction from a front surface (upper plane) of the semiconductor substrate (103); and wherein a lower end of the contact region (left 115) is deeper than a lower end of the contact trench portion, to achieve desired contact resistances with the contact region (Naito; [0093]).
Response to Arguments
Applicant’s arguments, see pages 8-12, filed 5/11/2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a new interpretation of prior art of record Pfirsch et al (US 2013/0270632 A1-of record, hereafter Pfirsch) in view of Herbert et al (US 2009/0218620 A1-of record, hereafter Herbert).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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