DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I and Species 1 in the reply filed on March 26 2026 is acknowledged. Claim 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention and/or Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 26 2026. Claims 1-15 are examined.
The Restriction/Election Requirement is made final.
Claim Objections
Claim 14 is objected to because of the following informalities:
“a backside contact in contact a backside surface of the source epi” is grammatically incorrect.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhou (US 2020/0044046).
Regarding claim 1, Zhou discloses a microelectronic structure (Figure 14) comprising:
a nanosheet transistor (see fin sheets in Figure 14), wherein the nanosheet transistor includes a source epi (252) and a drain epi (251);
a first inner spacer (209) located adjacent to the source epi (252, see Figure 14), wherein the first inner spacer (209) has a first width (D2, see Figure 11) as measured perpendicular to a gate direction (here the gate direction is into/out of the page in Figure 14, which is perpendicular to the horizontal direction of Figure 11); and
a second inner spacer (208) located adjacent to the drain epi (251, see Figure 14), wherein the second inner spacer (208) has second width (D1) as measured perpendicular to the gate direction (see Figure 11, which shows the widths of the spacers measured in the horizontal direction which is perpendicular to the in/out of the page, or the gate, direction), wherein the first width (D2) and the second width (D1) are different (see Figure 11 and para. [0100]).
Regarding claim 2, Zhou discloses wherein the first width (D2) is smaller than the second width (D1, see Figure 11 and para. [0100]).
Regarding claim 3, Zhou discloses wherein the first width (D2) is in the range of about 1 nm to 4 nm (see para. [0103] which discloses that the range of thickness for D2 may be 1.5-3 nm).
Regarding claim 4, Zhou discloses wherein the second width (D1) is in the range of about 5 nm to 8 nm (see para. [0102] which discloses that the range of thickness for D1 may be 2.5-5 nm, which overlaps with the claimed range at the endpoint, thus Zhou discloses the thickness of the second width D1 to be 5nm).
Regarding claim 5, Zhou discloses a microelectronic structure (Figure 14) comprising:
a nanosheet transistor (see sheets of fin channels, Figure 14), wherein the nanosheet transistor includes a source epi (252) and a drain epi (251), wherein the nanosheet transistor includes a plurality of channel layers (211);
a first inner spacer (209) located adjacent to the source epi (252, see Figure 14), wherein the first inner spacer (209) has a first width (D2) as measured perpendicular to a gate direction (the width is measured horizontally in Figure 11, and the gate direction is in/out of the page); and
a second inner spacer (208) located adjacent to the drain epi (251), wherein the second inner spacer (208) has second width (D1) as measured perpendicular to the gate direction (width D1 is measured horizontally which is perpendicular to the in/out direction), wherein the first width (D2) and the second width (D1) are different (see Figure 11 and para. [0100]).
Regarding claim 6, Zhou discloses wherein a sidewall of the drain epi (251) is in direct contact with the channel layers (211) and the second inner spacer (208, see Figure 14), wherein the sidewall of the drain epi (251) is a straight vertical surface (see Figure 14).
Regarding claim 10, Zhou discloses wherein the first width (D2) is smaller than the second width (D1, see Figure 11 and para. [0100]).
Regarding claim 11, Zhou discloses wherein the first width (D2) is in the range of about 1 nm to 4 nm (see para. [0103] which discloses that the range of thickness for D2 may be 1.5-3 nm).
Regarding claim 12, Zhou discloses wherein the second width (D1) is in the range of about 5 nm to 8 nm (see para. [0102] which discloses that the range of thickness for D1 may be 2.5-5 nm, which overlaps with the claimed range at the endpoint, thus Zhou discloses the thickness of the second width D1 to be 5nm).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou as applied to claim 5 above, and further in view of Chung et al. (“Chung” US Patent No. 11,227,917)
Regarding claim 7, Zhou does not disclose wherein a sidewall of the source epi includes a plurality of source epi protrusions.
Chung discloses in Figures 7C and 8C, however, wherein a sidewall of the source epi (261A/262A, see Figures 7C and 8C) includes a plurality of source epi protrusions (see Figures 7C and 8C, which shows protrusions of the source epi 261A/262A extending laterally to contact surfaces 297A/298A of the channel/semiconductor layers).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Chung into the teachings of Zhou to include the sidewall of the source epi having a plurality of source epi protrusions for the purpose of mitigating current crowding (see Chung, col. 20 line 52 to col. 21 line 6).
Regarding claim 8, Chung discloses wherein at least a top surface of the source epi protrusion (portion of the source epi 261A/262A in contact with the surface 298A, see Figure 7C) is in contact with a bottom surface (298A) of a channel layer (215, see Figures 7C and 8C).
Regarding claim 9, The combination of Zhou and Chung discloses wherein a sidewall of the source epi protrusion (protrusions of source epi 261A/262A of Chung incorporated into the source epi 252 of Zhou) is in contact with the first inner spacer (209 of Zhou, incorporating the protrusions of the source epi from Chung into the source epi of Zhou results in a structure where the protrusion will contact the upper and lower surfaces of the channel layers, as taught by Chung, as well as contact the inner spacers, as taught by Zhou).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou as applied to claim 5 above, and further in view of Kim et al. (“Kim” US 2024/0321688).
Regarding claim 13, Zhou does not explicitly disclose a source or drain contact.
Kim discloses, however, a frontside contact (135, see Figure 2 and para. [0039]) in contact with a frontside surface of the drain epi (150 in contact with 135, see Figure 2).
It would have obvious to a person having ordinary skill in the art to incorporate the teachings of Kim into the teachings of Zhou to include the frontside contact in contact with the frontside surface of the drain epi for the purpose of providing external electrical connection, as well as to reduce routing congestion (see Kim, para. [0024]).
Regarding claim 14, Kim discloses a backside contact (125, see Figure 2 and para. [0041]) in contact a backside surface of the source epi (150 in contact with 125, see Figure 2).
Similarly to above regarding claim 13, it would have obvious to a person having ordinary skill in the art to incorporate the teachings of Kim into the teachings of Zhou to include the backside contact in contact with the backside of the source epi for the purpose of providing external electrical connection, as well as to reduce routing congestion (see Kim, para. [0024]). Utilizing both the frontside and backside of the device for electrical connection to the drain epi and source epi, respectively, reducing routing congestion relative to a device where both contacts of the source/drain epis are located on the same side of the device.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Zhou as applied to claim 5 above, and further in view of Xie et al. (“Xie” US 2023/0095447).
Regarding claim 15, Zhou discloses that the inner spacers are formed of the same material (see initial spacer layer 207 which is etched back to form the inner spacers 208/209).
Xie discloses, however, wherein the first inner spacer (112 around the source structure 108) and the second inner spacer (110 around the drain structure 106) are comprised of different materials (see para. [0029], [0031]), wherein the first inner spacer (112) includes a first material that has a first dielectric constant K value (see para. [0029], [0031]), wherein the second inner spacer (110) includes a second material that has a second dielectric constant K value (see para. [0029], [0031]), and wherein the first dielectric constant K value is higher than the second dielectric constant K value (para. [0031] discloses that the spacers 110 have lower k-values than the spacers 112).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Xie into the teachings of Zhou to include the k-values for the spacers as claimed above for the purpose of optimizing capacitance in the nanosheet transistor structure (Xie, para. [0031]). Additionally, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Conclusion
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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