Prosecution Insights
Last updated: October 01, 2026
Application No. 18/513,736

OPTIMIZED INNER SPACER WITH BACKSIDE CONTACT

Final Rejection §103§112
Filed
Nov 20, 2023
Examiner
BULLARD-CONNOR, GENEVIEVE GRACE
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
2 (Final)
46%
Grant Probability
Moderate
3-4
OA Rounds
1y 0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 46% of resolved cases
46%
Career Allowance Rate
11 granted / 24 resolved
-22.2% vs TC avg
Strong +41% interview lift
Without
With
+41.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 10m
Avg Prosecution
41 currently pending
Career history
75
Total Applications
across all art units

Statute-Specific Performance

§103
53.7%
+13.7% vs TC avg
§102
28.6%
-11.4% vs TC avg
§112
17.7%
-22.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 24 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 1 and 5 are objected to because of the following informalities: “wherein first inner spacer” in claims 1 and 5 should read as “wherein the first inner spacer”, “nanoseheet” in claims 1 and 5 should read as “nanosheet”, and “has second width” in claim 5 should read as “has a second width”. Appropriate correction is required. Claim Rejections - 35 USC § 112 Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites both nanosheets and channel layers, however it is unclear whether these are in reference to the same element or if the claimed nanosheets are different from the disclosed/claimed channel layers (element 113). Based on the claim language of claim 5 alone, it seems that they are in reference to different elements, but based on the disclosure and terms of art, the Examiner believes the channel layers and the nanosheets to be in reference to the same element. Further, the limitations of claims 5, and 8 and 9, which depend indirectly on claim 5, seem to be pointing to the same disclosed feature where protrusions of the source epi and the inner spacers adjacent thereto contact the same surface of the channel layers (or the nanosheets if the channel layers are the same element as the nanosheets, see Figure 13). The Examiner suggests amending claim 5 to either refer to only the channel layers, or amend claim 5 and its dependent claims to refer to only the nanosheets as these are believed to be the same element. If this interpretation is incorrect and no amendment to address this issue is made, then the Examiner may apply a 112(a) rejection to the claims, since the feature of the source protrusions contacting the same surface of the disclosed channel layers (113) and the same surface of some other group of nanosheets is not supported by the disclosure, and may pose some indefiniteness issues as well. It is also possible that Applicant may be referring to different groups of the disclosed channel layers, i.e. where the claimed channel layers are a first plurality of the disclosed channel layers (113) and the claimed nanosheets are a second plurality of the disclosed channel layers. This level of speculation is indicative of an indefiniteness issue. For Examination purposes, the Examiner will interpret the nanosheets to be the same element as the channel layers. Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (“Park” US 2024/0421189) and Zhou et al. (“Zhou” US 2020/0044046). Regarding claim 1, Park discloses a microelectronic structure (Figures 1, 2, 8) comprising: a nanosheet transistor (see Figure 2), wherein the nanosheet transistor includes a source epi (160, left) and a drain epi (160, right), wherein the nanosheet transistor further includes a plurality of nanosheets (111/112/113); a first inner spacer (145, left) located adjacent to and in direct contact with the source epi (160, left), wherein the first inner spacer (145, left) has a first width (TH1) as measured perpendicular to a gate direction (see Figure 8, gate direction is in/out of the page in Figures 2 and 8, vertical direction in Figure 1), wherein the source epi (160, left) is in direct contact with a lateral horizontal surface of each of the plurality of nanosheets (111-113, the lateral horizontal surface being the lower surface of nanosheet 112 and upper surface of nanosheet 111 in Figure 8, and so on), wherein first inner spacer (145, left) is in direct contact with the lateral horizontal surface of the nanoseheet (see Figure 8, the source epi and the first inner spacers are in contact with the same surface of the nanosheets due to the protrusion of the source epi between nanosheets 111-113); and a second inner spacer (145, right) located adjacent to the drain epi (160, right, see Figure 2), wherein the second inner spacer (145, right) has second width (TH1) as measured perpendicular to the gate direction (see Figure 8, gate direction is in/out of the page in Figures 2 and 8, vertical direction in Figure 1). Park does not disclose wherein the first width and the second width are different. Zhou discloses, however, a source epi (252) and a drain epi (251), a first inner spacer (209) adjacent to the source epi (see Figure 14) and having a first width (D2), and a second inner spacer (208) adjacent to the drain epi (251) and having second width (D1), wherein the first width and the second width are different (see Figure 9, para. [0123], [0126], [0128]). It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Zhou into the teachings of Park to include different widths for the purpose of having the source epi relatively close to the gate structure for strong channel control, and having the drain epi relatively far from the gate structure to decrease parasitic capacitance between the gate and drain (Zhou, para. [0123]). Regarding claim 2, Zhou discloses wherein the first width (D2) is smaller than the second width (D1, see Figure 11 and para. [0100]). Regarding claim 3, Zhou discloses wherein the first width (D2) is in the range of about 1 nm to 4 nm (see para. [0103] which discloses that the range of thickness for D2 may be 1.5-3 nm). It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Zhou into the teachings of Park to include a width of 1 to 4 nm for the inner spacer adjacent to the source epi for the purpose of having the source epi relatively close to the gate structure for strong channel control (Zhou, para. [0123]). Regarding claim 4, Zhou discloses wherein the second width (D1) is in the range of about 5 nm to 8 nm (see para. [0102] which discloses that the range of thickness for D1 may be 2.5-5 nm, which overlaps with the claimed range at the endpoint, thus Zhou discloses the thickness of the second width D1 to be 5nm). It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Zhou into the teachings of Park to include a width of the inner spacer adjacent to the drain epi to be 5 to 8 nm for the purpose of having the drain epi relatively far from the gate structure to decrease parasitic capacitance between the gate and drain (Zhou, para. [0123]). Regarding claim 5, Park discloses a microelectronic structure comprising: a nanosheet transistor (see Figure 2), wherein the nanosheet transistor includes a source epi (160, left) and a drain epi (160, right), wherein the nanosheet transistor further includes a plurality of channel layers (111/112/113, see para. [0041]), wherein the nanosheet transistor further includes a plurality of nanosheets (111/112/113); a first inner spacer (145, left) located adjacent to and in direct contact with the source epi (160, left), wherein the first inner spacer (145, left) has a first width (TH1) as measured perpendicular to a gate direction (see Figure 8, gate direction is in/out of the page in Figures 2 and 8, vertical direction in Figure 1), wherein the source epi (160, left) is in direct contact with a lateral horizontal surface of each of the plurality of nanosheets (111-113, the lateral horizontal surface being the lower surface of nanosheet 112 and upper surface of nanosheet 111 in Figure 8, and so on), wherein first inner spacer (145, left) is in direct contact with the lateral horizontal surface of the nanoseheet (see Figure 8, the source epi and the first inner spacers are in contact with the same surface of the nanosheets due to the protrusion of the source epi between nanosheets 111-113); and a second inner spacer (145, right) located adjacent to the drain epi (160, right, see Figure 2), wherein the second inner spacer (145, right) has second width (TH1) as measured perpendicular to the gate direction (see Figure 8, gate direction is in/out of the page in Figures 2 and 8, vertical direction in Figure 1). Park does not disclose wherein the first width and the second width are different. Zhou discloses, however, a source epi (252) and a drain epi (251), a first inner spacer (209) adjacent to the source epi (see Figure 14) and having a first width (D2), and a second inner spacer (208) adjacent to the drain epi (251) and having second width (D1), wherein the first width and the second width are different (see Figure 9, para. [0123], [0126], [0128]). It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Zhou into the teachings of Park to include different widths for the purpose of having the source epi relatively close to the gate structure for strong channel control, and having the drain epi relatively far from the gate structure to decrease parasitic capacitance between the gate and drain (Zhou, para. [0123]). Regarding claim 6, Park discloses wherein a sidewall of the drain epi (160, right, left sidewall) is in direct contact with the channel layers (111-113) and the second inner spacer (145, right, see Figure 2). Park does not disclose wherein the sidewall of the drain epi is a straight vertical surface (Figure 8 shows a straight vertical surface of the drain epi in contact with the channel layers, however the vertical surface of the drain epi in contact with the inner spacer 145 is convex). Zhou discloses wherein a sidewall of the drain epi (251, right sidewall) is in direct contact with the channel layers (211) and the second inner spacer (208, see Figure 14), wherein the sidewall of the drain epi (251) is a straight vertical surface (see Figure 14). It would have been obvious to a person having ordinary skill in the art to incorporate the straight vertical sidewalls of the drain epi of Zhou into the teachings of Park. The specific limitation absent any criticality is only considered to be an obvious modification of the sidewall shape of the drain epi of Park, as the courts have held that changes in shape absent any critical aspect are within the level of skill in the art. According to the courts, a particular shape is nothing more than one among numerous configurations a person having ordinary skill in the art will find obvious to use under routine experimentation. See MPEP 2144(IV)(B) In re Dailey, 149 USPQ 47 (CCPA 1976). Regarding claim 7, Park discloses wherein a sidewall of the source epi (160, left) includes a plurality of source epi protrusions (see Figure 8). Regarding claim 8, Park discloses wherein at least a top surface of the source epi protrusion (see Figure 8) is in contact with a bottom surface of a channel layer (112, see Figure 8). Regarding claim 9, Park discloses wherein a sidewall of the source epi protrusion (see Figure 8) is in contact with the first inner spacer (145, left, see Figure 8). Regarding claim 10, Zhou discloses wherein the first width (D2) is smaller than the second width (D1, see Figure 11 and para. [0100]). Regarding claim 11, Zhou discloses wherein the first width (D2) is in the range of about 1 nm to 4 nm (see para. [0103] which discloses that the range of thickness for D2 may be 1.5-3 nm). It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Zhou into the teachings of Park to include a width of 1 to 4 nm for the inner spacer adjacent to the source epi for the purpose of having the source epi relatively close to the gate structure for strong channel control (Zhou, para. [0123]). Regarding claim 12, Zhou discloses wherein the second width (D1) is in the range of about 5 nm to 8 nm (see para. [0102] which discloses that the range of thickness for D1 may be 2.5-5 nm, which overlaps with the claimed range at the endpoint, thus Zhou discloses the thickness of the second width D1 to be 5nm). It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Zhou into the teachings of Park to include a width of the inner spacer adjacent to the drain epi to be 5 to 8 nm for the purpose of having the drain epi relatively far from the gate structure to decrease parasitic capacitance between the gate and drain (Zhou, para. [0123]). Regarding claim 13, Park further discloses a frontside contact (CA1) in contact with a frontside surface of the drain epi (160, right, see Figure 2). Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Park and Zhou as applied to claim 5 above, and further in view of Kim et al. (“Kim” US 2024/0321688). Regarding claim 14, Park does not disclose a backside contact in contact with the source epi. Kim discloses a backside contact (125, see Figure 2 and para. [0041]) in contact with a backside surface of the source epi (150 in contact with 125, see Figure 2). Similarly to above regarding claim 13, it would have obvious to a person having ordinary skill in the art to incorporate the teachings of Kim into the teachings of Park and Zhou to include the backside contact in contact with the backside of the source epi for the purpose of providing external electrical connection, as well as to reduce routing congestion (see Kim, para. [0024]). Utilizing both the frontside and backside of the device for electrical connection to the drain epi and source epi, respectively, reducing routing congestion relative to a device where both contacts of the source/drain epis are located on the same side of the device. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park and Zhou as applied to claim 5 above, and further in view of Xie et al. (“Xie” US 2023/0095447). Regarding claim 15, Park discloses that the inner spacers are formed of the same material (145, see Figure 2). Xie discloses, however, wherein the first inner spacer (112 around the source structure 108) and the second inner spacer (110 around the drain structure 106) are comprised of different materials (see para. [0029], [0031]), wherein the first inner spacer (112) includes a first material that has a first dielectric constant K value (see para. [0029], [0031]), wherein the second inner spacer (110) includes a second material that has a second dielectric constant K value (see para. [0029], [0031]), and wherein the first dielectric constant K value is higher than the second dielectric constant K value (para. [0031] discloses that the spacers 110 have lower k-values than the spacers 112). It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Xie into the teachings of Park and Zhou to include the k-values for the spacers as claimed above for the purpose of optimizing capacitance in the nanosheet transistor structure (Xie, para. [0031]). Response to Arguments Applicant’s arguments with respect to claim(s) 1 and 5 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Nov 20, 2023
Application Filed
May 07, 2026
Non-Final Rejection mailed — §103, §112
Jul 30, 2026
Applicant Interview (Telephonic)
Jul 30, 2026
Examiner Interview Summary
Aug 03, 2026
Response Filed
Aug 21, 2026
Final Rejection mailed — §103, §112
Sep 28, 2026
Interview Requested

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Prosecution Projections

3-4
Expected OA Rounds
46%
Grant Probability
87%
With Interview (+41.4%)
3y 10m (~1y 0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 24 resolved cases by this examiner. Grant probability derived from career allowance rate.

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