Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Applicant’s Response to Election/Restriction Requirement received on June 19, 2026, regarding the application filed November 23, 2023.
Election/Restrictions
Applicant’s election without traverse of Invention I, corresponding to claims 1-19 in the reply filed on June 19, 2026 is acknowledged. Claim 20 has been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. This restriction requirement has been finalized.
Claims 1-20 are pending, with claim 20 currently withdrawn from consideration.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 20, 2023 has been placed in the application file and is being considered by the examiner.
Drawings
The drawings filed with the application on November 20, 2023 are accepted.
Claim Objections
Claims 7 and 17 are objected to because of the following informalities: “wherein” has been inadvertently omitted. For examination purposes, claims 7 and 17 will be interpreted as “wherein a first sidewall of the isolation layer is in contact with both the shallow trench isolation layer and the signal contact.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 10 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lilak et al., US 2022/0352032 A1 (hereinafter Lilak).
Regarding claim 1, Lilak discloses: A microelectronic structure comprising: a first nanosheet transistor that includes a first source/drain (Lilak, FIG. 1B, leftmost instance of source/drain regions 124A, [0025]; nanowires, nanoribbons, nanosheets recognized as equivalents, [0020]);
a second nanosheet transistor that is adjacent to the first nanosheet transistor, wherein the second nanosheet transistor includes a second source/drain (Lilak, FIG. 1B, center instance of source/drain regions 124A, [0018; 0025]);
a shared gate that extends between the first nanosheet transistor and the second nanosheet transistor (Lilak, FIG. 1B shows gate, including gate dielectric 122A and gate electrode 120A, extending between leftmost instance of source/drain region 124A [the first nanosheet transistor] and center instance of source/drain region 124A [the second nanosheet transistor], [0016-0017]);
a gate protrusion that extends towards a backside region of the first nanosheet transistor and the backside region of the second nanosheet transistor (Lilak, FIGs. 9B-9D, conductor 328, shown extending toward backside contact region 103);
a first backside contact connected to the first source/drain (Lilak, FIG. 1B, leftmost instance of contact 138, shown connected to leftmost instance of source/drain regions 124A [the first source/drain], “contacts 138 are formed on the backside of source/drain regions 124A,” [0031]) and a second backside contact connected to the second source/drain (Lilak, FIG. 1B, center instance of contact 138, shown connected to center instance of source/drain regions 124A [the second source/drain], [0031]);
a signal contact connected to the gate protrusion (Lilak, FIGs. 9B-9D, center interconnect 968a, shown connected to conductor 928 [the gate protrusion], [0063]); and
an isolation layer located between the signal contact and first backside contact (Lilak, FIGs. 9A-9D, dielectric spacer 126 [the isolation layer] shown between center interconnect 968a [the signal contact] and leftmost instance of contact 138 [the first backside contact], [0031; 0057]) and the isolation layer is located between the signal contact and the second backside contact (Lilak, FIGs. 9A-9D, dielectric spacer 126 [the isolation layer] shown between center interconnect 968a [the signal contact] and rightmost instance of contact 138 [the second backside contact], [0031; 0057]).
Regarding claim 2, Lilak discloses: The microelectronic structure of claim 1, wherein a top surface of the first backside contact and a top surface of the signal contact are on different levels (Lilak, FIG. 9B, when viewed in the same orientation as Applicant’s FIG. 41, with backside contact region 103 at the top of the page, the top surface of leftmost instance of contact 138 [the first backside contact] and the top surface of center interconnect 968a [the signal contact] are on different levels; Lilak discloses that the technique of backside contact formation and the re-orientation of the semiconductor substrate to enable processing on the backside was known in the art, [0011]).
Regarding claim 3, Lilak discloses: The microelectronic structure of claim 1, further comprising: a signal line in direct contact with a top surface of the signal contact (Lilak, FIG. 9B shows conductor 328 [the signal line] in direct contact with a top surface of center interconnect 968a [the signal contact], [0050]; “the internal conductor can be used for routing power and signals,” i.e., a signal line, [0032]).
Regarding claim 4, Lilak discloses: The microelectronic structure of claim 1, wherein the isolation layer (Lilak, FIGs. 9A-9D, dielectric spacer 126) extends higher than a top surface of the first backside contact or a top surface of the second backside contact (Lilak, FIG. 9C, when viewed in the same orientation as Applicant’s FIG. 41, with backside contact region at the top of the page, the top surface of dielectric spacer 126 [the isolation layer] extends higher than a top surface of leftmost instance of contact 138 [the first backside contact] and top surface of center instance of contact 138 [the second backside contact]).
Regarding claim 10, Lilak discloses: A microelectronic structure comprising: a first nanosheet transistor that includes a first source/drain (Lilak, FIG. 1B, leftmost instance of source/drain regions 124A, [0025]; nanowires, nanoribbons, nanosheets recognized as equivalents, [0020]);
a second nanosheet transistor that is adjacent to the first nanosheet transistor, wherein the second nanosheet transistor includes a second source/drain (Lilak, FIG. 1B, center instance of source/drain regions 124A, [0018; 0025]);
a shared gate that extends between the first nanosheet transistor and the second nanosheet transistor (Lilak, FIG. 1B shows gate, including gate dielectric 122A and gate electrode 120A, extending between leftmost instance of source/drain region 124A [the first nanosheet transistor] and center instance of source/drain region 124A [the second nanosheet transistor], [0016-0017]);
a gate protrusion that extends towards a backside region of the first nanosheet transistor and the backside region of the second nanosheet transistor (Lilak, FIGs. 9B-9D, conductor 328, shown extending toward backside contact region 103);
a first backside contact connected to the first source/drain (Lilak, FIG. 1B, leftmost instance of contact 138, shown connected to leftmost instance of source/drain regions 124A [the first source/drain], “contacts 138 are formed on the backside of source/drain regions 124A,” [0031]) and a second backside contact connected to the second source/drain (Lilak, FIG. 1B, center instance of contact 138, shown connected to center instance of source/drain regions 124A [the second source/drain], [0031]);
a first metal line connected to the first backside contact (Lilak, FIG. 9B, leftmost instance of interconnect 968B [the first metal line] shown connected to leftmost instance of contact 138 [the first backside contact], [0063-0065]) and a second metal line connected to the second backside contact (Lilak, FIG. 9B, rightmost instance of interconnect 968B [the second metal line] shown connected to rightmost instance of contact 138 [the second backside contact], [0065]);
a signal contact connected to the gate protrusion (Lilak, FIGs. 9B-9D, center interconnect 968a, shown connected to conductor 928 [the gate protrusion], [0063]); and
an isolation layer located between the signal contact and first backside contact (Lilak, FIGs. 9A-9D, dielectric spacer 126 [the isolation layer] shown between center interconnect 968a [the signal contact] and leftmost instance of contact 138 [the first backside contact], [0031; 0057]) and the isolation layer is located between the signal contact and the second backside contact (Lilak, FIGs. 9A-9D, dielectric spacer 126 [the isolation layer] shown between center interconnect 968a [the signal contact] and rightmost instance of contact 138 [the second backside contact], [0031; 0057]).
Regarding claim 11, Lilak discloses: The microelectronic structure of claim 10, wherein a top surface of the first backside contact and a top surface of the signal contact are on different levels (Lilak, FIG. 9B, when viewed in the same orientation as Applicant’s FIG. 41, with backside contact region 103 at the top of the page, the top surface of leftmost instance of contact 138 [the first backside contact] and the top surface of center interconnect 968a [the signal contact] are on different levels).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-9 and 12-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al., US 2022/0352032 A1 (hereinafter Lilak) in view of Xie et al., US 2022/0301878 A1 (hereinafter Xie).
Regarding claims 5 and 16, Lilak discloses nearly every element of claims 5 and 16 but is silent regarding: a shallow trench isolation layer located between the first backside contact and the second backside contact.
However, Xie, in the same field of endeavor, teaches that it was known in the art before the effective filing date of the claimed invention that “STI (also known as a box isolation technique) is an integrated circuit feature which prevents electric current leakage between adjacent semiconductor device components,” and that the location of the STI layer “may be varied in any suitable manner according to the specific application,” (Xie, FIG. 5, STI layer 112 shown extending horizontally between leftmost instance of via 116 [the first backside contact] and rightmost instance of via 116 [the second backside contact], [0048-0049]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lilak with the teachings of Xie, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as recognized by Xie, to use shallow trench isolation (STI) to prevent current leakage between the first backside contact and the second backside contact and adjacent features, thereby improving device performance and reliability.
Regarding claim 6, Lilak in view of Xie teaches: The microelectronic structure of claim 5, wherein the signal contact is in contact with a top surface of the shallow trench isolation layer (Xie, FIG. 5 shows center instance of via 116 [analogous to the center interconnect 968a of Lilak, i.e., the signal contact] in contact with top surface of STI layer 112 [the shallow trench isolation layer]).
Regarding claims 7 and 17, Lilak in view of Xie teaches: wherein a first sidewall of the isolation layer (Lilak, FIGs. 9A-9D, dielectric spacer 126; Xie, FIG. 5, dielectric layer 122, [0050]) is in contact with both the shallow trench isolation layer and the signal contact (Xie, FIG. 5 shows portion of dielectric layer 122 on the left side of center instance of via 116 [the first sidewall of the isolation layer] in contact with both STI layer 112 [the shallow trench isolation layer] and center instance of via 116 [the signal contact]).
Regarding claim 8, Lilak in view of Xie teaches: The microelectronic structure of claim 7, further comprising: a backside interlayer dielectric layer located above the first backside contact and the second backside contact (Lilak, FIG. 9B, when viewed in the same orientation as Applicant’s FIG. 41, with backside contact region 103 at the top of the page, the interlayer dielectric layer 966 [the backside interlayer dielectric layer] is shown located above leftmost instance of contact 138 [the first backside contact] and rightmost instance of contact 138 [the second backside contact]).
Regarding claim 9, Lilak in view of Xie teaches: The microelectronic structure of claim 8, wherein a second sidewall of the isolation layer (Lilak, FIGs. 9A-9D, dielectric spacer 126; Xie, FIG. 5, dielectric layer 122, [0050]) is in contact with the backside interlayer dielectric layer and the first backside contact or the second backside contact, respectively (Xie, FIG. 5 shows portion of dielectric layer 122 on the right side of center instance of via 116 [the second sidewall of the isolation layer] in contact with rightmost instance of via 116 [the second backside contact]).
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Lilak in view of Xie include one or more of Applicant’s claimed alternative elements, for example: a second sidewall of the isolation layer is in contact with the second backside contact.
Regarding claim 12, Lilak in view of Xie teaches: The microelectronic structure of claim 11, further comprising: a signal line in direct contact with a top surface of the signal contact (Xie, FIG. 5 shows center instance of contact 120 [the signal line] in direct contact with a top surface of via 116 [analogous to the center interconnect 968a of Lilak, i.e., the signal contact]).
Regarding claim 13, Lilak in view of Xie teaches: The microelectronic structure of claim 12, wherein the signal line, the first metal line and the second metal line are on the same level (Xie, FIG. 5 shows center instance of contact 120 [the signal line], leftmost instance of contact 120 [the first metal line] and rightmost instance of contact 120 [the second metal line] are on the same level).
Regarding claim 14, Lilak in view of Xie teaches nearly every element of claim 14 but is silent regarding: a first connecting via connecting the first metal line to the first backside contact and a second connecting via connecting the second metal line to the second backside contact. However, Xie recognizes that “any suitable number/position/configuration of these layers may be used. In other words, the different metal layers, contacts, vias etc., are merely provided to show a nonlimiting example,” (Xie, [0050]). Therefore it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply the knowledge generally available to one of ordinary skill in the art, with a high likelihood of success and without undue experimentation, to arrive at Applicant’s claimed first connecting via connecting the first metal line to the first backside contact and a second connecting via connecting the second metal line to the second backside contact. The motivation for doing so would be, as recognized by Xie, to provide for electrical connection between different features, thereby enabling device functionality.
Regarding claim 15, Lilak in view of Xie teaches: The microelectronic structure of claim 14, wherein the isolation layer (Lilak, FIGs. 9A-9D, dielectric spacer 126) extends higher than a top surface of the first backside contact or a top surface of the second backside contact (Lilak, FIG. 9, when viewed in the same orientation as Applicant’s FIG. 41, with backside contact region at the top, the top surface of dielectric spacer 126 [the isolation layer] extends higher than a top surface of leftmost instance of contact 138 [the first backside contact] and top surface of center instance of contact 138 [the second backside contact]).
Regarding claim 18, Lilak in view of Xie teaches: The microelectronic structure of claim 17, further comprising: a backside interlayer dielectric layer located above the first backside contact and the second backside contact (Lilak, FIG. 9B, when viewed in the same orientation as Applicant’s FIG. 41, with backside contact region 103 at the top of the page, the interlayer dielectric layer 966 [the backside interlayer dielectric layer] is shown located above leftmost instance of contact 138 [the first backside contact] and rightmost instance of contact 138 [the second backside contact]).
Regarding claim 19, Lilak in view of Xie teaches: The microelectronic structure of claim 18, wherein a second sidewall of the isolation layer (Lilak, FIGs. 9A-9D, dielectric spacer 126; Xie, FIG. 5, dielectric layer 122, [0050]) is in contact with the backside interlayer dielectric layer and the first backside contact or the second backside contact, respectively (Xie, FIG. 5 shows portion of dielectric layer 122 on the right side of center instance of via 116 [the second sidewall of the isolation layer] in contact with rightmost instance of via 116 [the second backside contact]).
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Lilak in view of Xie include one or more of Applicant’s claimed alternative elements, for example: a second sidewall of the isolation layer is in contact with the second backside contact.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure. The cited prior art discloses similar materials, devices, and methods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRENT A FAIRBANKS can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights