Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsuboi (US 20240147624).
Regarding claim 10, Tsuboi discloses an interposer circuit board (circuit board 200) comprising:
a first pair of conductive paths (a pair of conductive path comprising pads 230 or 230E, 230G) having a first spacing to create a radio frequency (RF) transmission line (a space between the pads and the wiring of the wiring component, paragraph 44); and
a first pair of electrical interconnect pads (the pads 230E and 230G) having solderable surfaces configured to be electrically coupled to an integrated circuit device (the semiconductor device 100) using solder connections (solder ball 350E), wherein the first pair of electrical interconnect pads have a second spacing greater than the first spacing (Fig. 11B);
wherein the first pair of electrical interconnect pads are electrically coupled to the RF transmission line (the wiring of the wiring components are inherently connect to the pads to form the circuitry), the first pair of electrical interconnect pads being noncircular and elongated (Fig. 11B) on a common axis and are configured, during a solder reflow process, to cause solder to flow in a direction of the common axis to form an RF transition between the integrated circuit device and the interposer circuit board (solders flow along the path of the elongated pad, Fig. 11A & 11B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 – 6, 8, 11, 13 – 15, 21 - 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuboi (US 20240147624).
Regarding claim 1, Tsuboi discloses a system comprising:
an integrated circuit device (a semiconductor 100) having a first pair of electrical interconnect pads (pads 130) with solderable surfaces; and
an interposer circuit board (circuit board 200) having a second pair of electrical interconnect pads (pad 230) with solderable surfaces,
the second pair of electrical interconnect pads being configured to provide electrical coupling to the first pair of electrical interconnect pads through solder connections (solder ball 350), and having a first pair of conductive paths (a pair of path connected to members 350E and 350G, Fig. 11B; and the wiring of the wiring component, paragraph 44) spaced to create a radio frequency (RF) transmission line (the transmission path formed by the pair of path connected to the elongated members 350E and 350G, Fig. 11B; and the wiring of the wiring component, paragraph 44), wherein the first pair of conductive paths are electrically coupled to the second pair of electrical interconnect pads (350E, 350G).
Tsuboi does not explicitly disclose the first pair of electrical interconnect pads are noncircular and elongated on a common axis and are configured, during a solder reflow process, to cause solder to flow in a direction of the common axis to form an RF transition between the integrated circuit device and the interposer circuit board.
Tsuboi suggests the pads (350E, 350G; Fig. 11B) are noncircular and elongated into a connection path to transmit signals and/or power.
It would have been obvious to one having skill in the art at the effective filing date of the invention to modify the shape of the working components in order to optimize the connection between the components and the circuit board.
Regarding claim 2, Tsuboi discloses the claimed invention as set forth in claim 1. Tsuboi further suggests the first pair of electrical interconnect pads are elongated directly toward each other on the common axis (Fig. 11B).
Regarding claim 3, Tsuboi discloses the claimed invention as set forth in claim 1. Tsuboi further suggests the first pair of electrical interconnect pads are elongated at an angle relative to the common axis (Fig. 11B), to provide a component of elongation on the common axis (Fig. 11B).
Regarding claim 4, Tsuboi discloses the claimed invention as set forth in claim 1. Tsuboi further suggests the first pair of electrical interconnect pads are arranged according to a first pitch, the second pair of electrical interconnect pads are arranged according to a second pitch, and the first pitch and second pitch are equal (the pitch between the pads 130 and between pads 230 are equal, Fig. 3).
Regarding claim 5, Tsuboi discloses the claimed invention as set forth in claim 1. Tsuboi further suggests the first pair of electrical interconnect pads are arranged according to a first pitch, the second pair of electrical interconnect pads are arranged according to a second pitch, and the first pitch and second pitch are unequal (the pitch between pads 130 and between pads 230 may not be equal depend upon the shape of the pad, Fig. 17B).
Regarding claim 6, Tsuboi discloses the claimed invention as set forth in claim 1. Tsuboi further suggests the integrated circuit device includes a bare integrated circuit (the component 100 appears to be a bare component) die, and wherein the first pair of electrical interconnect pads are formed on the bare integrated circuit die (the pads 130 are formed on the component 100).
Regarding claim 8, Tsuboi discloses the claimed invention as set forth in claim 1. Tsuboi further suggests the first pair of electrical interconnect pads are noncircular and elongated (as suggested in claim 1 comment), and wherein the RF transition between the integrated circuit device and the interposer circuit board is formed between the first pair of electrical interconnect pads and the second pair of electrical interconnect pads (the pads are between the semiconductor chip and the circuit board, conducting signal/power therebetween).
Regarding claim 11, Tsuboi discloses the claimed invention as set forth in claim 10.
Tsuboi does not explicitly disclose a plurality of noncircular, elongated pairs of electrical interconnect pads, and wherein the first pair of electrical interconnect pads is one of the plurality of noncircular, elongated pairs of electrical interconnect pads.
Tsuboi suggests the pads (350E, 350G; Fig. 11B) are noncircular and elongated into a connection path to transmit signals and/or power.
It would have been obvious to one having skill in the art at the effective filing date of the invention to modify the shape of the working components in order to optimize the connection between the components and the circuit board.
Regarding claim 13, Tsuboi discloses the claimed invention as set forth in claim 10. Tsuboi further discloses a plurality of electrical interconnect pads arranged in a pattern corresponding to an arrangement of contacts of a ball grid array (BGA, Fig. 11B) package, wherein the plurality of electrical interconnect pads comprise the first pair of electrical interconnect pads (230E).
Regarding claim 14, Tsuboi discloses the claimed invention as set forth in claim 10. Tsuboi further discloses the first pair of electrical interconnect pads are elongated directly toward each other on the common axis (Fig. 11B).
Regarding claim 15, Tsuboi discloses the claimed invention as set forth in claim 10. Tsuboi further suggests the first pair of electrical interconnect pads are elongated at an angle relative to the common axis, to provide a component of elongation on the common axis (Fig. 11B).
Regarding claim 21, Tsuboi discloses a method comprising:
fabricating an interposer circuit board (circuit board 200) having a first pair of conductive paths (the path comprising the pads 230E, Fig. 11B, and the wirings; paragraph 44) spaced to form a radio frequency (RF) transmission line (the wirings of the components; paragraph 44), and having a first pair of electrical interconnect pads (pads 230E) with solderable surfaces being noncircular and elongated on a common axis, wherein the first pair of electrical interconnect pads are electrically coupled to the RF transmission line (pads of the components connected to the wirings to form a circuitry); and
electrically coupling an integrated circuit device (100) to the interposer circuit board.
Tsuboi does not explicitly disclose the electrically coupling comprises performing a solder reflow operation to allow solder to flow in a direction of the common axis of the first pair of electrical interconnect pads.
Tsuboi suggests the elongated pads 230E having solder ball covered the surface (Fig. 11B).
It would have been obvious to one having skill in the art at the effective filing date of the invention to adjust the shape of the components including the flow of the material to form the shape of the component in order to provide a proper connection between components in the circuit board.
Regarding claim 22, Tsuboi discloses the claimed invention as set forth in claim 21. Tsuboi further discloses the integrated circuit device includes a pair of circular electrical interconnect pads (pad 130 or 130E) spaced to be electrically coupled to the first pair of electrical interconnect pads on the interposer circuit board.
Regarding claim 23, Tsuboi discloses the claimed invention as set forth in claim 21.
Tsuboi does not explicitly disclose the integrated circuit device includes a pair of noncircular electrical interconnect pads spaced to be electrically coupled to the first pair of electrical interconnect pads on the interposer circuit board.
Tsuboi suggests the pads (350E, 350G; Fig. 11B) are noncircular and elongated into a connection path to transmit signals and/or power.
It would have been obvious to one having skill in the art at the effective filing date of the invention to modify the shape of the working components in order to optimize the connection between the components and the circuit board.
Allowable Subject Matter
Claims 16 – 20 are allowed.
Claim 7, 9, 12, 24 - 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 7, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that the integrated circuit device comprises: a bare integrated circuit die; a polymer layer formed on the bare integrated circuit die, wherein the polymer layer includes a plurality of conductive traces to redistribute electrical connections from the bare integrated circuit die; and a metallization layer formed on the polymer layer, wherein the metallization layer includes the first pair of electrical interconnect pads having solderable surfaces. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 9, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that the interposer circuit board includes an RF launcher electrically coupled to the RF transmission line on the interposer circuit board. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 12, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 10, a combination of limitations that an RF launcher electrically coupled to the RF transmission line. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 16, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 16, a combination of limitations that a radio frequency (RF) circuit configured to produce RF energy. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 24, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 21, a combination of limitations that molding over an integrated circuit die to produce a molded integrated circuit device, wherein the integrated circuit die includes an RF circuit configured to produce RF energy; forming a polymer layer on the molded integrated circuit device, wherein the polymer layer includes a second plurality of conductive paths to redistribute interconnects on the molded integrated circuit device to a ball grid array pattern having a pitch compatible with the interposer circuit board, wherein a second pair of the second plurality of conductive paths are electrically coupled to conduct the RF energy; and forming a metallization layer on the polymer layer to form the integrated circuit device, wherein the metallization layer includes a second pair of electrical interconnect pads electrically coupled to the second pair of the second plurality of conductive paths on the polymer layer to conduct the RF energy, wherein the second pair of electrical interconnect pads are spaced to be electrically coupled to the first pair of electrical interconnect pads on the interposer circuit board during the solder reflow operation to form an RF transition between the integrated circuit device and the interposer circuit board. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen (US 20170005052) discloses an elongated pad, Fig. 1C.
Rostoker (US 5300815) discloses an elongated pad, Fig. 3C.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH B TRAN/Primary Examiner, Art Unit 2848