DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species C, claims 1-20 in the reply filed on 03/23/2026 is acknowledged.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2023-0007238, filed on 01/18/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/20/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102 as being anticipated by Park et al. ( US 8,836,142 B2; hereinafter Park )
Regarding claim 1, Park teaches a semiconductor package ( Fig. 20 ), comprising: a package substrate ( Fig. 20: package board 200 ); a first semiconductor chip ( Fig. 20: semiconductor device 100 ) stacked on the package substrate ( Fig. 19 #200 ), the first semiconductor chip ( Fig. 20 #100 ) comprising: a first substrate ( Fig. 1: semiconductor substrate 10 ) having first ( Fig. 1 first surface 1 ) and second surfaces ( Fig. 1 second surface 2b ) opposite to each other ( as shown in Fig. 1 ), a plurality of electrode bundles ( Fig. 1 #20 and #60 ) each comprising a plurality of through electrodes ( Fig. 1 #20 ) that are adjacent to each other ( as shown in Fig. 1 ), the plurality of through electrodes penetrating the first substrate ( Fig. 1 #20 penetrates the substrate of #10 ), a backside insulating layer ( Fig. 13: pad insulating layer 61 ) on the second surface ( Fig. 13 #2b) of the first substrate ( Fig. 13 #10 ) through which end portions of the plurality of through electrodes are exposed ( Fig. 13 #20 ), and a plurality of electrode pads ( Fig. 2 first connecting pad 35 ) respectively provided on the plurality of electrode bundles ( as shown in Fig. 2 ); a second semiconductor chip ( Fig. 20 #300 ) stacked on the first semiconductor chip ( Fig. 20 #100 ) by way of conductive bumps ( Fig. 20: connecting terminals 170 ) ; and an adhesive layer filling a space between the conductive bumps ( Fig. 20: molding layer 500 ) between the first semiconductor chip ( Fig. 20 #100 ) and the second semiconductor chip ( Fig. 20 #300 ), the adhesive layer ( Fig. 20 #500 ) attaching the first semiconductor chip ( Fig. 20 #100 ) to the second semiconductor chip ( Fig. 20 #300 ), wherein the backside insulating layer ( Fig. 13 #61 ) has a first trench ( Fig. 2: pad trench 53 ) formed between the end portions of the plurality of through electrodes ( Fig. 20 #20 ) of a first electrode bundle ( Fig. 20 #20 left side figure ) of the plurality of electrode bundles ( Fig. 20 #20 ), wherein a first electrode pad ( Fig. 2 #35 ) of the plurality of electrode pads is electrically connected to the plurality of through electrodes ( Fig. 20 #20 ) of the first electrode bundle ( Fig. 20 #20 left side of figure ) of the plurality of electrode bundles, and wherein the first electrode pad ( Fig. 2 #35 ) has a protruding portion that fills the first trench of the backside insulating layer ( Fig. 2 #35 is connected to the electrode 20 which is also connected to the trench 53 ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under U.S.C. 103 as being unpatentable over Park et al.; US 8,836,142 B2; 06/2013 in view of Kijima; US 2024/0347408 A1; 09/2022
Claim 2: Park discloses the semiconductor package of claim 1 ( as discussed above ), wherein the backside insulating layer ( Fig. 2 #61 ) comprises: a first passivation layer ( Fig. 17: passivation layer 75 ) covering the second surface ( Fig. 17 second surface 2b ) of the first substrate ( Fig. 17 #10 ) and sidewalls of the end portions of the plurality of through electrodes protruding from the second surface ( Fig. 17 second connecting pad 70 );
Park does not appear to disclose a second passivation layer formed on the first passivation layer.
However, Kijima teaches a second passivation layer ( Fig. 2 second passivation layer 60 ) formed on the first passivation layer ( Fig. 2 first passivation layer 50 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kijima with Park to implement a second passivation layer formed on the first passivation layer because these layers can reduce charge recombination at surface states and protect the semiconductor from chemical corrosion.
Claims 3 and 4 are rejected under U.S.C. 103 as being unpatentable over Park et al.; US 8,836,142 B2; 06/2013 in view of Kijima; US 2024/0347408 A1; 09/2022 as it relates to claim 2 above and further in view of Curatola et al.; US 2019/0280100 A1; 03/2018
Claim 3: Park and Kijima disclose the semiconductor package of claim 2 ( as discussed above ).
Neither Park nor Kijima appear to disclose the first trench is provided in the second passivation layer between adjacent through electrodes of the plurality of through electrodes in the first electrode bundle.
However, Curatola teaches the first trench ( Fig. 14: first and second trenches 176, 178 ) is provided in the second passivation layer ( Fig. 14: second passivation layer 130 ) between adjacent through electrodes of the plurality of through electrodes in the first electrode bundle ( Fig. 14 #120 and #118 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Curatola with Park and Kijima to implement the first trench is provided in the second passivation layer between adjacent through electrodes of the plurality of through electrodes in the first electrode bundle because this approach provides electrical isolation between electrodes and structural separation for manufacturability.
Claim 4: Park, Kijima, and Curatola disclose the semiconductor package of claim 3 ( as discussed above ),
Neither Park nor Kijima appear to disclose the first passivation layer is exposed through a bottom face of the trench.
However, Curatola teaches the first passivation layer ( Fig. 10 first passivation layer 128 ) is exposed ( as shown in Fig. 10 ) through a bottom face of the trench ( Fig. 10 #178 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Curatola with Park and Kijima to implement the first passivation layer is exposed through a bottom face of the trench because this implements process control and layer sequencing.
Claim 5 is rejected under U.S.C. 103 as being unpatentable over Park et al.; US 8,836,142 B2; 06/2013 in view of Kijima; US 2024/0347408 A1; 09/2022 and Curatola et al.; US 2019/0280100 A1; 03/2018 as it relates to claim 3 above and further in view of Ma; US 2022/0392859 A1; 04/2022
Claim 5: Park, Kijima, and Curatola disclose the semiconductor package of claim 3 ( as discussed above).
Neither Park nor Kijima nor Curatola appear to disclose an upper surface of the second passivation layer is positioned on the same plane as an exposed surface of the end portion of the plurality of through electrodes.
However, Ma teaches an upper surface of the second passivation layer ( Fig. 25: second passivation layer 205 ) is positioned on the same plane as an exposed surface of the end portion of the plurality of through electrodes ( Fig. 25: second connective pad 207 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ma with Park, Kijima, and Curatola to implement an upper surface of the second passivation layer is positioned on the same plane as an exposed surface of the end portion of the plurality of through electrodes because this approach facilitates electrical isolation and protection along with mechanical stability and stress management.
Claims 6 and 7 are rejected under U.S.C. 103 as being unpatentable over Park et al.; US 8,836,142 B2; 06/2013 in view of Shao et al.; US 2024/0063079 A1; 04/2022
Claim 6: Park discloses the semiconductor package of claim 1 ( as discussed above).
Park does not appear to disclose a depth of the trench is within a range of 0.5 µm to 2.5 µm.
However, Shao teaches a depth of the trench ( Fig. 19: trenches 84 ) is within a range of 0.5 µm to 2.5 µm ( [0049] referring to FIG. 19, each of the trenches 84 may have a width W ranging from 2 μm to 3000 μm and a depth D ranging from 1 μm to 1000 μm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Shao with Park to implement a depth of the trench is within a range of 0.5 µm to 2.5 µm because the trench depth is a critical design parameter that balances electrical performance, mechanical stability, and manufacturabilty.
Claim 7: Park discloses the semiconductor package of claim 1 ( as discussed above).
Park does not appear to disclose a width of the trench is within a range of 1 µm to 3 µm.
However, Shao teaches a width of the trench ( Fig. 19: trenches 84 ) is within a range of 1 µm to 3 µm ( [0049] referring to FIG. 19, each of the trenches 84 may have a width W ranging from 2 μm to 3000 μm and a depth D ranging from 1 μm to 1000 μm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Shao with Park to implement a width of the trench is within a range of 1 µm to 3 µm because this approach balances electrical performance, manufacturability, and process control.
Claims 8 is rejected under U.S.C. 103 as being unpatentable over Park et al.; US 8,836,142 B2; 06/2013 in view of Kim et al.; US 2023/0029098 A1; 04/2022
Claim 8: Park discloses the semiconductor package of claim 1 ( as discussed above).
Park does not appear to disclose the second semiconductor chip is disposed such that the second semiconductor chip faces the first surface of the first substrate.
However, Kim (‘098) teaches the second semiconductor chip is disposed such that the second semiconductor chip faces the first surface of the first substrate ( [0029] The second semiconductor chip 200 may be positioned such that a lower surface 201B of a second substrate 201 of the second semiconductor chip 200 faces the upper surface 101T of the first substrate 101 of the first semiconductor chip 100 )
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim (‘098) with Park to implement the second semiconductor chip is disposed such that the second semiconductor chip faces the first surface of the first substrate because this approach maximizes interconnect density, improves electrical performance, and enables compact, high-performance packaging.
Claims 9, 10, and 18-19 are rejected under U.S.C. 103 as being unpatentable over Park et al.; US 8,836,142 B2; 06/2013 in view of Kim et al.; US 2023/0378110 A1; 12/2022
Claim 9: Park discloses the semiconductor package of claim 1 ( as discussed above).
Park does not appear to disclose the first semiconductor chip further comprises: a backside wiring layer on the backside insulating layer, the backside wiring layer comprising metal wirings electrically connected to the plurality of electrode pads; and a plurality of second bonding pads on the backside wiring layer and electrically connected to the metal wirings.
However, Kim (‘110) teaches the first semiconductor chip ( Fig. 14: semiconductor chip 200’ ) further comprises: a backside wiring layer ( Fig. 14: first chip wiring layer 220 ) on the backside insulating layer ( [0089] The first chip passivation layer 224 may include an insulating material. For example, the first chip passivation layer 224 may include silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON) ), the backside wiring layer ( Fig. 14 #220 ) comprising metal wirings ( [0089] The first chip pads 222 may include a conductive material such as metal ) electrically connected to the plurality of electrode pads ( Fig. 14: first chip pads 222 ); and a plurality of second bonding pads ( [0093] The first chip pads 222 and the second chip pads 232 may form intermetallic hybrid bonding with each other ) on the backside wiring layer ( Fig. 14 #220 ) and electrically connected to the metal wirings ( [0093] The semiconductor chips 200 may be electrically connected to each other through the first chip pads 222 and the second chip pads 232 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim (‘110) with Park to implement the first semiconductor chip further comprises: a backside wiring layer on the backside insulating layer, the backside wiring layer comprising metal wirings electrically connected to the plurality of electrode pads; and a plurality of second bonding pads on the backside wiring layer and electrically connected to the metal wirings because this approach reduces IR drop and improves power integrity, frees frontside wiring for signals, and enhances thermal management.
Claim 10: Park and Kim (‘110) disclose the semiconductor package of claim 9 ( as discussed above).
Park teaches the conductive bumps ( Fig. 20: external connecting terminals 240 ) are bonded to the plurality of second bonding pads ( Fig. 20: ball pads 230 ) respectively.
Claim 18: Park discloses the semiconductor package of claim 11 ( as discussed above).
Park does not appear to disclose the first semiconductor chip further comprises: a backside wiring layer on the backside insulating layer, the backside wiring layer comprising metal wirings electrically connected to the plurality of electrode pads; and a plurality of second bonding pads on the backside wiring layer and electrically connected to the metal wirings.
However, Kim teaches the first semiconductor chip ( Fig. 14: semiconductor chip 200’ ) further comprises: a backside wiring layer ( Fig. 14: first chip wiring layer 220 ) on the backside insulating layer ( [0089] The first chip passivation layer 224 may include an insulating material. For example, the first chip passivation layer 224 may include silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON) ), the backside wiring layer ( Fig. 14 #220 ) comprising metal wirings ( [0089] The first chip pads 222 may include a conductive material such as metal ) electrically connected to the plurality of electrode pads ( Fig. 14: first chip pads 222 ); and a plurality of second bonding pads ( [0093] The first chip pads 222 and the second chip pads 232 may form intermetallic hybrid bonding with each other ) on the backside wiring layer ( Fig. 14 #220 ) and electrically connected to the metal wirings ( [0093] The semiconductor chips 200 may be electrically connected to each other through the first chip pads 222 and the second chip pads 232 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim (‘110) with Park to implement the first semiconductor chip further comprises: a backside wiring layer on the backside insulating layer, the backside wiring layer comprising metal wirings electrically connected to the plurality of electrode pads; and a plurality of second bonding pads on the backside wiring layer and electrically connected to the metal wirings because of limitations of traditional frontside power delivery, concept of backside power delivery, the advantages of backside wiring, and enhanced thermal management.
Claim 19: Park and Kim (‘110) disclose the semiconductor package of claim 18 ( as discussed above).
Park teaches the conductive bumps ( Fig. 20: external connecting terminals 240 ) are bonded to the plurality of second bonding pads ( Fig. 20: ball pads 230 ) respectively.
Claim 11 and 17 are rejected under U.S.C. 103 as being unpatentable over Park et al.; US 8,836,142 B2; 06/2013 in view of Lee et al.; US 12,628,658 B2; 11/2022
Claim 11: Park discloses a semiconductor package, comprising: a first semiconductor chip ( Fig. 20 semiconductor device 100 ) comprising: a first substrate ( Fig. 1 semiconductor substrate 10 ) having first and second surfaces opposite to each other ( as shown in Fig. 1 ), a plurality of electrode bundles ( Fig. 1 #20 and #60 ) arranged in an array in the first substrate ( Fig. 1 #10 ), each of the plurality of electrode bundles ( Fig. 1 #20 and #60 ) comprising a plurality of through electrodes ( Fig. 1 #20 ) penetrating the first substrate ( Fig. 1 #10 ), a plurality of first bonding pads ( Fig. 1: first connecting pad 35 ) on the first surface of the first substrate ( Fig. 1 #10 ) and electrically connected to the plurality of through electrodes ( Fig. 1 #20 ), a backside insulating layer ( Fig. 13: pad insulating layer 61 ) on the second surface ( Fig. 1 #2b ) of the first substrate ( Fig. 1 #10 ) through which end portions of the plurality of through electrodes are exposed ( Fig. 1 #20 ), and a plurality of electrode pads ( Fig. 1: second connecting pad 70 ) respectively provided on the plurality of electrode bundles ( Fig. 1 #20 and #60 );
Park does not appear to disclose a second semiconductor chip comprising a second substrate having first and second surfaces opposite to each other and a plurality of third bonding pads provided on the first surface of the second substrate, the second semiconductor chip being stacked on the first semiconductor chip by way of conductive bumps formed on the third bonding pads respectively, wherein the backside insulating layer has a first trench formed between the plurality of through electrodes of a first electrode bundle of the plurality of electrode bundles, and wherein a first electrode pad is disposed on the plurality of through electrodes of the first electrode bundle and comprises a protruding portion that fills the first trench of the backside insulating layer.
However, Lee teaches a second semiconductor chip ( Fig. 3: second semiconductor chip 200 ) comprising a second substrate ( Fig. 3 second substrate 202 ) having first and second surfaces opposite to each other ( as shown in Fig. 3 ) and a plurality of third bonding pads ( Fig. 3: second bottom connection pads 210 ) provided on the first surface ( as shown in Fig. 3 ) of the second substrate ( Fig 3 #202), the second semiconductor chip ( Fig. 3 #200 ) being stacked on the first semiconductor chip ( Fig. 3: first semiconductor chip 100 ) by way of conductive bumps ( Fig. 3 #240 ) formed on the third bonding pads ( Fig. 3 #210 ) respectively, wherein the backside insulating layer ( Fig. 3 protective insulating layer 300 ) has a first trench formed between the plurality of through electrodes of a first electrode bundle of the plurality of electrode bundles ( Col. 1 line 56 – Col. 2 line 8 the protective insulating layer contacting the plurality of first chip connection bumps or the plurality of second chip connection bumps, and a first dummy conductive structure at a bottom surface of each second semiconductor chip of the plurality of second semiconductor chips ), and wherein a first electrode pad ( Fig. 3: first bottom connection pads 110 ) is disposed on the plurality of through electrodes ( Fig. 3: first through electrodes 130 ) of the first electrode bundle ( Fig. 3 #110, #130 and #120 ) and comprises a protruding portion ( Fig. 3 #120 ) that fills the first trench ( Fig. 3 area to the left side where #240 is placed ) of the backside insulating layer ( Fig. 3 #300 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Park to implement a second semiconductor chip comprising a second substrate having first and second surfaces opposite to each other and a plurality of third bonding pads provided on the first surface of the second substrate, the second semiconductor chip being stacked on the first semiconductor chip by way of conductive bumps formed on the third bonding pads respectively, wherein the backside insulating layer has a first trench formed between the plurality of through electrodes of a first electrode bundle of the plurality of electrode bundles, and wherein a first electrode pad is disposed on the plurality of through electrodes of the first electrode bundle and comprises a protruding portion that fills the first trench of the backside insulating layer because this approach overcomes the limitations of traditional frontside power delivery.
Claim 17: Park and Lee disclose the semiconductor package of claim 11 ( as discussed above ).
Park does not appear to disclose the first surface of the second substrate faces the second surface of the first substrate.
However, Lee teaches the first surface ( Fig. 2: bottom surface of 202 ) of the second substrate ( Fig. 2: second substrate 202 ) faces the second surface ( Fig. 2: top surface of 102 ) of the first substrate ( Fig. 2: first substrate 102 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Park to implement the first surface of the second substrate faces the second surface of the first substrate because this enables direct electrical and mechanical connections via solder balls while optimizing signal routing and thermal management.
Claim 12 and 20 are rejected under U.S.C. 103 as being unpatentable over Park et al.; US 8,836,142 B2; 06/2013 in view of Lee et al.; US 12,628,658 B2; 11/2022 as it relates to claim 11 above and further in view of Kijima; US 2024/0347408 A1; 09/2022
Claim 12: Park and Lee disclose the semiconductor package of claim 11 ( as discussed above ), wherein the backside insulating layer ( Fig. 2 #61 ) comprises: a first passivation layer ( Fig. 17: passivation layer 75 ) covering the second surface ( Fig. 17 second surface 2b ) of the first substrate ( Fig. 17 #10 ) and sidewalls of the end portions of the plurality of through electrodes protruding from the second surface ( Fig. 17 second connecting pad 70 ); N
Neither Park nor Lee appear to disclose a second passivation layer formed on the first passivation layer.
However, Kijima teaches a second passivation layer ( Fig. 2 second passivation layer 60 ) formed on the first passivation layer ( Fig. 2 first passivation layer 50 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kijima with Park and Lee to implement a second passivation layer formed on the first passivation layer because this approach is used to protect the underlying semiconductor and metal features from environmental factors, electrical stress, and mechanical damage.
Claim 20: Park discloses a semiconductor package, comprising: a first semiconductor chip ( Fig. 20 semiconductor device 100 ) comprising: a first substrate ( Fig. 1 semiconductor substrate 10 ) having first and second surfaces opposite to each other ( as shown in Fig. 1 ), a plurality of electrode bundles ( Fig. 1 #20 and #60 ) arranged in an array in the first substrate ( Fig. 1 #10 ), each of the plurality of electrode bundles ( Fig. 1 #20 and #60 ) comprising a plurality of through electrodes ( Fig. 1 #20 ) penetrating the first substrate ( Fig. 1 #10 ), a plurality of first bonding pads ( Fig. 1: first connecting pad 35 ) on the first surface of the first substrate ( Fig. 1 #10 ) and electrically connected to the plurality of through electrodes ( Fig. 1 #20 ), a backside insulating layer ( Fig. 13: pad insulating layer 61 ) on the second surface ( Fig. 1 #2b ) of the first substrate ( Fig. 1 #10 ) through which end portions of the plurality of through electrodes are exposed ( Fig. 1 #20 ), and a plurality of electrode pads ( Fig. 1: second connecting pad 70 ) respectively provided on the plurality of electrode bundles ( Fig. 1 #20 and #60 ); and a sealing member ( Fig. 20 molding layer 500 ) on the first semiconductor chip ( Fig. 20 first semiconductor device 100 ) covering a side surface ( as shown in Fig. 20 ) of the second semiconductor chip ( Fig. 20 second semiconductor chip 300 ) , wherein the backside insulating layer ( Fig. 2: interlayer insulating layer 33 ) comprises: a first passivation layer ( Fig. 2: passivation layer 37 ) covering the second surface of the first substrate ( Fig. 2: semiconductor substrate 10 ) and sidewalls of the end portions of the plurality of through electrodes ( Fig. 2 through-electrode 20 ) protruding from the second surface ( as shown in Fig. 2 ); an adhesive layer ( Fig. 17 metal base layer 72 ) filling a space between the conductive bumps ( Fig. 17 bump 74 ) between the first semiconductor chip ( Fig. 20 #100 ) and the second semiconductor chip ( Fig. 20 #300 ), the adhesive layer ( Fig. 17 #72 ) attaching the first semiconductor chip ( Fig. 20 #100 ) to the second semiconductor chip ( Fig. 20 #200 ) and having a first trench ( Fig. 2: pad trench 53 ) formed between the plurality of through electrodes ( Fig. 2: through-electrodes 20 ) of a first electrode bundle ( as shown in Fig. 2 ), and wherein a first electrode pad ( Fig. 2: first connecting pad 35 ) is disposed on the plurality of through electrodes ( Fig. 2 #20 ) of the first electrode bundle ( as shown in Fig. 2 ) and comprises a protruding portion ( Fig. 2 #35 ) that fills the first trench of the second passivation layer ( Fig. 2: passivation layer 37 )
Park does not appear to disclose a second semiconductor chip stacked on the first semiconductor chip by way of conductive bumps; and a second passivation layer formed on the first passivation layer
Lee discloses a second semiconductor chip ( Fig. 3: second semiconductor chip 200 ) stacked on the first semiconductor chip ( Fig. 3: first semiconductor chip 100 ) by way of conductive bumps ( Fig. 3: #240 ) ;
Lee does not appear to disclose a second passivation layer formed on the first passivation layer.
However, Kijima teaches a second passivation layer ( Fig. 4: second passivation layer 60 ) formed on the first passivation layer ( Fig. 4: first passivation layer 50 )
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kijima with Park and Lee to implement a second semiconductor chip stacked on the first semiconductor chip by way of conductive bumps; and a second passivation layer formed on the first passivation layer because this provides short, direct electrical connections between chips replacing long wire bonds.
Claims 13 and 14 are rejected under U.S.C. 103 as being unpatentable over Park et al.; US 8,836,142 B2; 06/2013 in view of Lee et al.; US 12,628,658 B2; 11/2022 and Kijima; US 2024/0347408 A1; 09/2022 as is relates to claim 12 above and further in view of Curatola et al.; US 2019/0280100 A1; 03/2018
Claim 13: Park, Lee, and Kijima disclose the semiconductor package of claim 12 ( as discussed above ).
Neither Park nor Lee nor Kijima appear to disclose the first trench is provided in the second passivation layer between adjacent through electrodes of the plurality of through electrodes in the first electrode bundle.
However, Curatola teaches the first trench ( Fig. 14: first and second trenches 176, 178 ) is provided in the second passivation layer ( Fig. 14: second passivation layer 130 ) between adjacent through electrodes of the plurality of through electrodes in the first electrode bundle ( Fig. 14 #120 and #118 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Curatola with Park, Lee, and Kijima to implement the first trench is provided in the second passivation layer between adjacent through electrodes of the plurality of through electrodes in the first electrode bundle because this approach would prevent crack propagation, moisture penetration, and mechanical stress damage caused during die sawing or environmental exposure.
Claim 14: Park, Lee, Kijima, and Curatola disclose the semiconductor package of claim 13 ( as discussed above ),
Neither Park nor Lee nor Kijima appear to disclose the first passivation layer is exposed through a bottom face of the trench.
However, Curatola teaches the first passivation layer ( Fig. 10 first passivation layer 128 ) is exposed ( as shown in Fig. 10 ) through a bottom face of the trench ( Fig. 10 #178 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Curatola with Park, Lee, and Kijima to implement the first passivation layer is exposed through a bottom face of the trench because this approach allows for the attachment of solder balls.
Claim 15: Park, Lee, Kijima, and Curatola disclose the semiconductor package of claim 13 ( as discussed above).
Neither Park nor Lee nor Kijima nor Curatola appear to disclose an upper surface of the second passivation layer is positioned on the same plane as an exposed surface of the end portion of the plurality of through electrodes.
However, Ma teaches an upper surface of the second passivation layer ( Fig. 25: second passivation layer 205 ) is positioned on the same plane as an exposed surface of the end portion of the plurality of through electrodes ( Fig. 25: second connective pad 207 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ma with Park, Lee, Kijima, and Curatola to implement an upper surface of the second passivation layer is positioned on the same plane as an exposed surface of the end portion of the plurality of through electrodes because this implements surface passivation, interface passivation, and passivation layer positioning.
Claim 16: Park and Lee disclose the semiconductor package of claim 11 ( as discussed above).
Neither Park nor Lee appear to disclose a depth of the trench is within a range of 0.5 µm to 2.5 µm.
However, Shao teaches a depth of the trench ( Fig. 19: trenches 84 ) is within a range of 0.5 µm to 2.5 µm ( [0049] referring to FIG. 19, each of the trenches 84 may have a width W ranging from 2 μm to 3000 μm and a depth D ranging from 1 μm to 1000 μm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Shao with Park and Lee to implement a depth of the trench is within a range of 0.5 µm to 2.5 µm because the depth of the trench allows for optimal performance and efficiency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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