DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15, in the reply filed on March 26, 2026 is acknowledged. Claims 16-20 have been withdrawn. Action on the merits is as follows:
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 6-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kao et al. (Kao) (US 2021/0391302 A1).
In regards to claim 1, Kao (Fig. 1-4 and associated text and items) discloses a semiconductor structure (item 100), comprising: a substrate (item 108, 108c); a first active layer (item 108, 108c, paragraph 38, item 210 or 210 plus 108c) in the substrate (item 108, 108c); a second active layer (item 108, 108a, paragraph 38, item 210 or item 210 plus 108a) vertically over the first active layer (item 108, 108c, paragraph 38, item 210 or 210 plus 108c); a first interconnection structure (items 114 plus 116, 112c or 112c plus 120c) between the first active layer (item 108, 108c, paragraph 38, item 210 or 210 plus 108c) and the second active layer (item 108, 108a, paragraph 38, item 210 or item 210 plus 108a); a second interconnection structure (items 114 plus 116, 112a or 112a plus 120a) between the first interconnection structure (items 114 plus 116, 112c or 112c plus 120c) and the second active layer (item 108, 108a, paragraph 38, item 210 or item 210 plus 108a); a first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b) between the first interconnection structure (items 114 plus 116, 112c or 112c plus 120c) and the second interconnection structure (items 114 plus 116, 112a or 112a plus 120a); and a passive device (item 110b paragraph 38, capacitor, resistor) in the first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b).
In regards to claim 2, Kao (Fig. 1-4 and associated text and items) discloses wherein the passive device (item 110b paragraph 38, capacitor, resistor) is electrically connected to the first interconnection structure (items 114 plus 116, 112c or 112c plus 120c) and the second interconnection structure (items 114 plus 116, 112a or 112a plus 120a).
In regards to claim 3, Kao (Fig. 1-4 and associated text and items) discloses further comprising: a second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c) over the first active layer (item 108, 108c, paragraph 38, item 210 or 210 plus 108c), and the first interconnection structure (items 114 plus 116, 112c or 112c plus 120c) is in the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c); a third interlayer dielectric stack (item 118, 112a, 112a plus 120a or 118 plus 120a) between the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c) and the second active layer (item 108, 108a, paragraph 38, item 210 or 210 plus 108a), and the second interconnection structure (items 114 plus 116, 112a or 112a plus 120a) is in the third interlayer dielectric stack (item 118, 112a, 112a plus 120a or 118 plus 120a); and the first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b) is between the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c) and the third interlayer dielectric stack (item 118, 112a, 112a plus 120a or 118 plus 120a).
In regards to claim 4, Kao (Fig. 1-4 and associated text and items) discloses wherein the first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b)is in contact with the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c). Examiner notes the Applicant has not given a special definition to the term “contact”, therefore certain features can be in “direct” or “indirect” contact.
In regards to claim 6, Kao (Fig. 1-4 and associated text and items) discloses further comprising: a first active device (item 110c) in the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c); and a second active device (item 110a) in the third interlayer dielectric stack (item 118, 112a, 112a plus 120a or 118 plus 120a), and the passive device (item 110b) is between the first active device (item 110c) and the second active device (item 110a).
In regards to claim 7, Kao (Fig. 1-4 and associated text and items) discloses further comprising a first contact (item 122) extending between the first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b) and the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c).
In regards to claim 8, Kao (Fig. 1-4 and associated text and items) discloses wherein the first contact (item 122) includes a first conductive plug (item 122) in the first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b)and a second conductive plug (item 122) in the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c).
In regards to claim 9, Kao (Fig. 1-4 and associated text and items) discloses wherein the first conductive plug (item 122) is horizontally offset from the second conductive plug (item 122).
In regards to claim 10, Kao (Fig. 1-4 and associated text and items) discloses wherein the first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b) and the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c) each comprise a dielectric surface (surface of items 120b, 120c), and the dielectric surface of the first interlayer dielectric stack (surface of item 120b)adjoins the dielectric surface of the second interlayer dielectric stack (surface of item 120c) at a bonding interface (bonding interface of items 120b plus 120c).
In regards to claim 11, Kao (Fig. 1-4 and associated text and items) discloses wherein the first conductive plug (item 122) and the second conductive plug (item 122) each comprise a conductive surface (conductive surface of item 122), and the conductive surface of the first conductive plug (conductive surface of item 122) adjoins the conductive surface of the second conductive plug (conductive surface of item 122) at the bonding interface (bonding interface of items 120b plus 120c, hybrid bond).
In regards to claim 12, Kao (Fig. 1-4 and associated text and items) discloses wherein the bonding interface (bonding interface of items 120b plus 120c, hybrid bond) extends across the semiconductor structure (item 100).
In regards to claim 13, Kao (Fig. 1-4 and associated text and items) discloses further comprising: a dielectric layer (item 120a) between the first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b) and the third interlayer dielectric stack (item 118, 112a, 112a plus 120a or 118 plus 120a); and a second contact (items 122) extending between the dielectric layer (item 120a) and the third interlayer dielectric stack (item 118, 112a, 112a plus 120a or 118 plus 120a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (Kao) (US 2021/0391302 A1) in view of Lee et al. (Lee) (US 2022/0165712 A1, now US 11,862,618 B2).
In regards to claim 5, Kao (Fig. 1-4 and associated text and items) does not specifically disclose wherein a crystalline semiconductor material is absent between the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c) and the third interlayer dielectric stack (item 118, 112a, 112a plus 120a or 118 plus 120a).
Lee (Fig. 3, 9 and associated text) discloses a passive device (item CAP) in the first interlayer dielectric stack (item IMD) which does not contain crystalline semiconductor material.
Therefore it would have been obvious to one of ordinary skill in the art to before the effective filing date to incorporate the teachings of Lee for the purpose of an interlayer having decoupling capacitors and improve operation characteristics.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (Kao) (US 2021/0391302 A1) in view of Li et al. (Li) (US 2022/0293556 A1 now US 11,682,652 B2).
In regards to claim 14, Kao does not specifically disclose further comprising: a dielectric layer, wherein the second active layer is between the dielectric layer and the second interconnection structure; and a circuitry interconnection extending through the dielectric layer and electrically connected to the second interconnection structure.
Li (Fig. 16 and associated text) discloses further comprising: a dielectric layer (item 306, paragraph 33), wherein the second active layer (item 102b, active layer of transistor) is between the dielectric layer (item 306) and the second interconnection structure (item 412, 412 plus 428 or 412 plus 428 plus 430 ); and a circuitry interconnection (items 310 plus 312 plus 308) extending through the dielectric layer (item 306) and electrically connected to the second interconnection structure (item 412, 412 plus 428 or 412 plus 428 plus 430 ).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Li for the purpose of protection/insulation and an electrical connection.
In regards to claim 15, Kao as modified by Li (Fig. 16 and associated text) discloses wherein the circuitry interconnection (items 310 plus 312 plus 308) comprises a via structure (items 310, 308) extending through the dielectric layer (item 306) and a pad structure (item 312) on the dielectric layer (item 306).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See all references in 892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 May 11, 2026
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