DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed July 30, 2026 have been fully considered but they are not persuasive. Applicant argues on page 8 that Kao does specifically disclose “a passive device within the first interlayer dielectric stack” as recited in independent claim 1. The Examiner respectfully disagrees. The Examiner agrees that the passive device of Kao is partially within the substrate, however it is partially within the denoted first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b) of Kao as well. Examiner notes that the claim does not recite “a passive device completely within/completely embedded in or by/completely surrounded by the first interlayer dielectric stack”. The Examiner takes the position the rejection is proper.
Applicant’s arguments with respect to claim(s) 1-15 have been considered but are moot on grounds of new rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 6-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kao et al. (Kao) (US 2021/0391302 A1).
In regards to claim 1, Kao (Fig. 1-4 and associated text and items) discloses a semiconductor structure (item 100), comprising: a substrate (item 108, 108c); a first active layer (item 108, 108c, paragraph 38, item 210 or 210 plus 108c) in the substrate (item 108, 108c); a second active layer (item 108, 108a, paragraph 38, item 210 or item 210 plus 108a) vertically over the first active layer (item 108, 108c, paragraph 38, item 210 or 210 plus 108c); a first interconnection structure (items 114 plus 116, 112c or 112c plus 120c) between the first active layer (item 108, 108c, paragraph 38, item 210 or 210 plus 108c) and the second active layer (item 108, 108a, paragraph 38, item 210 or item 210 plus 108a); a second interconnection structure (items 114 plus 116, 112a or 112a plus 120a) between the first interconnection structure (items 114 plus 116, 112c or 112c plus 120c) and the second active layer (item 108, 108a, paragraph 38, item 210 or item 210 plus 108a); a first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b) between the first interconnection structure (items 114 plus 116, 112c or 112c plus 120c) and the second interconnection structure (items 114 plus 116, 112a or 112a plus 120a); and a passive device (item 110b paragraph 38, capacitor, resistor) within the first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b).
In regards to claim 2, Kao (Fig. 1-4 and associated text and items) discloses wherein the passive device (item 110b paragraph 38, capacitor, resistor) is electrically connected to the first interconnection structure (items 114 plus 116, 112c or 112c plus 120c) and the second interconnection structure (items 114 plus 116, 112a or 112a plus 120a).
In regards to claim 3, Kao (Fig. 1-4 and associated text and items) discloses further comprising: a second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c) over the first active layer (item 108, 108c, paragraph 38, item 210 or 210 plus 108c), and the first interconnection structure (items 114 plus 116, 112c or 112c plus 120c) is in the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c); a third interlayer dielectric stack (item 118, 112a, 112a plus 120a or 118 plus 120a) between the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c) and the second active layer (item 108, 108a, paragraph 38, item 210 or 210 plus 108a), and the second interconnection structure (items 114 plus 116, 112a or 112a plus 120a) is in the third interlayer dielectric stack (item 118, 112a, 112a plus 120a or 118 plus 120a); and the first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b) is between the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c) and the third interlayer dielectric stack (item 118, 112a, 112a plus 120a or 118 plus 120a).
In regards to claim 4, Kao (Fig. 1-4 and associated text and items) discloses wherein the first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b)is in contact with the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c). Examiner notes the Applicant has not given a special definition to the term “contact”, therefore certain features can be in “direct” or “indirect” contact.
In regards to claim 6, Kao (Fig. 1-4 and associated text and items) discloses further comprising: a first active device (item 110c) in the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c); and a second active device (item 110a) in the third interlayer dielectric stack (item 118, 112a, 112a plus 120a or 118 plus 120a), and the passive device (item 110b) is between the first active device (item 110c) and the second active device (item 110a).
In regards to claim 7, Kao (Fig. 1-4 and associated text and items) discloses further comprising a first contact (item 122) extending between the first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b) and the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c).
In regards to claim 8, Kao (Fig. 1-4 and associated text and items) discloses wherein the first contact (item 122) includes a first conductive plug (item 122) in the first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b)and a second conductive plug (item 122) in the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c).
In regards to claim 9, Kao (Fig. 1-4 and associated text and items) discloses wherein the first conductive plug (item 122) is horizontally offset from the second conductive plug (item 122).
In regards to claim 10, Kao (Fig. 1-4 and associated text and items) discloses wherein the first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b) and the second interlayer dielectric stack (item 118, 112c, 112c plus 120c or 118 plus 120c) each comprise a dielectric surface (surface of items 120b, 120c), and the dielectric surface of the first interlayer dielectric stack (surface of item 120b)adjoins the dielectric surface of the second interlayer dielectric stack (surface of item 120c) at a bonding interface (bonding interface of items 120b plus 120c).
In regards to claim 11, Kao (Fig. 1-4 and associated text and items) discloses wherein the first conductive plug (item 122) and the second conductive plug (item 122) each comprise a conductive surface (conductive surface of item 122), and the conductive surface of the first conductive plug (conductive surface of item 122) adjoins the conductive surface of the second conductive plug (conductive surface of item 122) at the bonding interface (bonding interface of items 120b plus 120c, hybrid bond).
In regards to claim 12, Kao (Fig. 1-4 and associated text and items) discloses wherein the bonding interface (bonding interface of items 120b plus 120c, hybrid bond) extends across the semiconductor structure (item 100).
In regards to claim 13, Kao (Fig. 1-4 and associated text and items) discloses further comprising: a dielectric layer (item 120a) between the first interlayer dielectric stack (item 118, 112b, 112b plus 108b, 118 plus 108b or 118 plus 108b plus 120b) and the third interlayer dielectric stack (item 118, 112a, 112a plus 120a or 118 plus 120a); and a second contact (items 122) extending between the dielectric layer (item 120a) and the third interlayer dielectric stack (item 118, 112a, 112a plus 120a or 118 plus 120a).
Claim(s) 1-8 and 10-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shen et al. (Shen) (US 2022/0285434 A1).
In regards to claim 1, Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses a semiconductor structure (items 10, 10’ or 100 plus 200), comprising: a substrate (items 110 or 210); a first active layer (layer/area between source/drain regions 114 or 214) in the substrate (items 110 or 210); a second active layer (layer/area between source/drain regions 114 or 214) vertically over the first active layer (layer/area between source/drain regions 114 or 214); a first interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226) between the first active layer (layer/area between source/drain regions 114 or 214) and the second active layer (layer/area between source/drain regions 114 or 214); a second interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226) between the first interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226) and the second active layer (layer/area between source/drain regions 114 or 214); a first interlayer dielectric stack (items 146 plus 246) between the first interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226) and the second interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226); and a passive device (items Cap1 or Cap1 plus Cap2, Figs. 3B, 4) within the first interlayer dielectric (items 146 plus 246).
In regards to claim 2, Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses wherein the passive device (items Cap1 or Cap1 plus Cap2) is electrically connected to the first interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226) and the second interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226).
In regards to claim 3, Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses further comprising: a second interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6) over the first active layer (layer/area between source/drain regions 114 or 214), and the first interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226) is in the second interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6); a third interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6) between the second interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6) and the second active layer (layer/area between source/drain regions 114 or 214), and the second interconnection structure ((items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226) is in the third interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6); and the first interlayer dielectric stack (items 146 plus 246) is between the second interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6) and the third interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6).
In regards to claim 4, Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses wherein the first interlayer dielectric stack (items 146 plus 246) is in contact with the second interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6). Examiner notes the Applicant has not given a special definition to the term “contact”, therefore certain features can be in “direct” or “indirect” contact.
In regards to claim 5, Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses wherein a crystalline semiconductor material is absent between the second interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6)and the third interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6).
In regards to claim 6, Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses further comprising: a first active device (item D1 or D2) in the second interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6); and a second active device (item D1 or D2) in the third interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6), and the passive device (items Cap1 or Cap1 plus Cap2) is between the first active device (item D1 or D2) and the second active device (item D1 or D2).
In regards to claim 7, Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses further comprising a first contact (items 150A-150C, 250A-260C or 150A-150C plus 250A-250C) extending between the first interlayer dielectric stack (items 146 plus 246) and the second interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6).
In regards to claim 8, Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses wherein the first contact (items 150A-150C, 250A-260C or 150A-150C plus 250A-250C) includes a first conductive plug (item 152A plus 154 or 252A plus 254) in the first interlayer dielectric stack (items 146 plus 246) and a second conductive plug (item 124-5 or 224-5) in the second interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6).
In regards to claim 10, Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses wherein the first interlayer dielectric stack (items 146 plus 246) and the second interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6) each comprise a dielectric surface (surface of items 246 and 222-6), and the dielectric surface (surface of item 246) of the first interlayer dielectric stack (items 146 plus 246) adjoins the dielectric surface (surface of 222-6) of the second interlayer dielectric stack (items 222-0 to 222-6) at a bonding interface (bonding interface of items 246 and 222-6, 252A plus 254 and 224-5).
In regards to claim 11, Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses wherein the first conductive plug (item 152A plus 154 or 252A plus 254) and the second conductive plug (item 124-5 or 224-5) each comprise a conductive surface (conductive surface of item 124-5 or 224-5 and 152A plus 154 or 252A plus 254), and the conductive surface of the first conductive plug (conductive surface of 152A plus 154 or 252A plus 254) adjoins the conductive surface of the second conductive plug (conductive surface of item 124-5 or 224-5) at the bonding interface (bonding interface of items 246 and 222-6, 252A plus 254 and 224-5).
In regards to claim 12, Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses wherein the bonding interface (bonding interface of items 246 and 222-6, 252A plus 254 and 224-5) extends across the semiconductor structure (items 10, 10’ or 100 plus 200).
In regards to claim 13, Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses further comprising: a dielectric layer (item 140, 122-7 or 140 plus 122-7) between the first interlayer dielectric stack (item 146 plus 246) and the third interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6); and a second contact (item 150A or 124-5 plus 126-5) extending between the dielectric layer (item 140, 122-7 or 140 plus 122-7) and the third interlayer dielectric stack (items 122-0 to 122-7 or 222-0 to 222-6).
In regards to claim 14, Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses further comprising: a dielectric layer (item 310), wherein the second active layer (layer/area between source/drain region 214) is between the dielectric layer (item 310) and the second interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226); and a circuitry interconnection (item 250 plus 252) extending through the dielectric layer (item 310) and electrically connected to the second interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226).
In regards to claim 15, Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses wherein the circuitry interconnection (items 250 plus 252) comprises a via structure (item 252 or 250 pus 252) extending through the dielectric layer (item 310) and a pad structure (item 304) on the dielectric layer (item 310).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. (Shen) (US 2022/0285434 A1) in view of Kao et al. (Kao) (US 2021/0391302 A1).
In regards to claim 9, Shen does not specifically disclose wherein the first conductive plug is horizontally offset from the second conductive plug.
In regards to claim 9, Kao (Fig. 1-4 and associated text and items) discloses wherein the first conductive plug (item 122) is horizontally offset from the second conductive plug (item 122).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kao for the purpose of an electrical connection and design choice.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (Kao) (US 2021/0391302 A1) in view of Li et al. (Li) (US 2022/0293556 A1 now US 11,682,652 B2).
In regards to claim 14, Kao does not specifically disclose further comprising: a dielectric layer, wherein the second active layer is between the dielectric layer and the second interconnection structure; and a circuitry interconnection extending through the dielectric layer and electrically connected to the second interconnection structure.
Li (Fig. 16 and associated text) discloses further comprising: a dielectric layer (item 306, paragraph 33), wherein the second active layer (item 102b, active layer of transistor) is between the dielectric layer (item 306) and the second interconnection structure (item 412, 412 plus 428 or 412 plus 428 plus 430 ); and a circuitry interconnection (items 310 plus 312 plus 308) extending through the dielectric layer (item 306) and electrically connected to the second interconnection structure (item 412, 412 plus 428 or 412 plus 428 plus 430 ).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Li for the purpose of protection/insulation and an electrical connection.
In regards to claim 15, Kao as modified by Li (Fig. 16 and associated text) discloses wherein the circuitry interconnection (items 310 plus 312 plus 308) comprises a via structure (items 310, 308) extending through the dielectric layer (item 306) and a pad structure (item 312) on the dielectric layer (item 306).
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. (Shen) (US 2022/0285434 A1) in view of Li et al. (Li) (US 2022/0293556 A1 now US 11,682,652 B2).
In regards to claim 14, Shen does not specifically disclose further comprising: a dielectric layer, wherein the second active layer is between the dielectric layer and the second interconnection structure; and a circuitry interconnection extending through the dielectric layer and electrically connected to the second interconnection structure.
Li (Fig. 16 and associated text) discloses further comprising: a dielectric layer (item 306, paragraph 33), wherein the second active layer (item 102b, active layer of transistor) is between the dielectric layer (item 306) and the second interconnection structure (item 412, 412 plus 428 or 412 plus 428 plus 430 ); and a circuitry interconnection (items 310 plus 312 plus 308) extending through the dielectric layer (item 306) and electrically connected to the second interconnection structure (item 412, 412 plus 428 or 412 plus 428 plus 430 ).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Li for the purpose of protection/insulation and an electrical connection.
In regards to claim 15, Shen as modified by Li (Fig. 16 and associated text) discloses wherein the circuitry interconnection (items 310 plus 312 plus 308) comprises a via structure (items 310, 308) extending through the dielectric layer (item 306) and a pad structure (item 312) on the dielectric layer (item 306).
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (Kao) (US 2021/0391302 A1) in view of Shen et al. (Shen) (US 2022/0285434 A1).
In regards to claim 1, Kao (Fig. 1-4 and associated text and items) discloses all of the limitations (see anticipatory rejection by Kao above) except a passive device (completely) within the first interlayer dielectric stack.
Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses a semiconductor structure (items 10, 10’ or 100 plus 200), comprising: a substrate (items 110 or 210); a first active layer (layer/area between source/drain regions 114 or 214) in the substrate (items 110 or 210); a second active layer (layer/area between source/drain regions 114 or 214) vertically over the first active layer (layer/area between source/drain regions 114 or 214); a first interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226) between the first active layer (layer/area between source/drain regions 114 or 214) and the second active layer (layer/area between source/drain regions 114 or 214); a second interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226) between the first interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226) and the second active layer (layer/area between source/drain regions 114 or 214); a first interlayer dielectric stack (items 146 plus 246) between the first interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226) and the second interconnection structure (items 120, 116 plus 118 plus 124 plus 126, 220 or 216 plus 218 plus 224 plus 226); and a passive device (items Cap1 or Cap1 plus Cap2, Figs. 3B, 4) (completely) within the first interlayer dielectric (items 146 plus 246).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Shen for the purpose of protection/insulation and an electrical connection.
In regards to claims 2-15, Kao (Fig. 1-4 and associated text and items) as modified by Shen (Fig. 1F, 2D, 3A, 3B, 4 and associated text and items) discloses the Applicant’s claimed invention (See anticipatory rejections of Kao and Shen above).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 August 31, 2026
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