Prosecution Insights
Last updated: October 25, 2026
Application No. 18/514,038

MASK INTEGRATION FOR TRENCHED SEMICONDUCTOR DEVICE STRUCTURES

Final Rejection §102
Filed
Nov 20, 2023
Examiner
CHANG, JAY C
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed Inc.
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
586 granted / 686 resolved
+17.4% vs TC avg
Moderate +14% lift
Without
With
+13.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
28 currently pending
Career history
723
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
42.2%
+2.2% vs TC avg
§102
28.1%
-11.9% vs TC avg
§112
27.2%
-12.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 686 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is responsive to the following communications: the Amendment filed 8/31/2026. Claims 1, 3-6, 8-9, 11-14, 16, 19, 21 and 39 are pending. Claim 8 is withdrawn. Claims 2, 7, 10, 15, 17-18, 20 and 22-38 are cancelled. Claim 39 is new. Claims 1, 14 and 19 are currently amended. Claims 1, 14 and 19 are independent. Response to Arguments Applicants’ arguments and amendments, filed 8/31/2026, with respect to Prior Art Rejections for independent claims 1 and 19, as indicated in line numbers 2-4 of the office action mailed 6/2/2026, have been fully considered and are persuasive. The rejections have been withdrawn. Applicants' arguments and amendments, filed 8/31/2026, with respect to independent claim 14, although substantive and pertinent to expediting the prosecution of the current application, are considered not persuasive, respectfully, for the reasons that follow. Regarding independent claim 14, the claim has been amended to recite “wherein the JFET region extends partially but not completely underneath the trenched gate structure” which applicants contend is not disclosed or taught by the prior art, including Kim (Remarks 10). Applicants’ contentions are fully considered, however are not found persuasive, since as noted below in the rejection of independent claim 14 Kim discloses “wherein the JFET region extends partially but not completely underneath the trenched gate structure”, since paragraph [0082] of Kim discloses that structure 240a may extend along only a portion of the bottom surface of gate trench 180 such that JFET region 175 extends underneath the outer edges of gate trench 180, which meets the claim limitation of JFET region extending partially but not completely under trenched gate structure 180. Thus, for the aforementioned reasons the rejection is deemed proper. Claim Objections Claims 1, 3-6, 9, 11-13 and 39 are objected to because of the following informalities: Claim 1 recites the limitation “the JFET region” in line 10 of the claim, which the Examiner suggests amending to “the first JFET region”, because it appears that the claimed element was originally introduced in line 2 of the claim using that specific language. Note the dependent claims 3-6, 9, 11-13 and 39 necessarily inherit the indefiniteness of the claims on which they depend. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim Rejections - 35 USC § 102 Claims 14, 16 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2023/0307529 A1, hereinafter “Kim”). Regarding independent claim 14, Figure 2 of Kim discloses a semiconductor device, comprising: a semiconductor layer structure comprising a junction field-effect transistor (JFET) region 175 (“JFET region”- ¶¶0065, 0067) of a first conductivity type (i.e., n-type- ¶0065), a well region 170 (“well regions”- ¶0067) of a second conductivity type (i.e., p-type- ¶0065) on the JFET region 175, a source region 160 (“source regions”- ¶0067) of the first conductivity type on the well region 170; and a trenched gate structure 180 (“gate trench”- ¶0075) formed in the semiconductor layer structure between a pair of adjacent support shields 240b (“shielding structures”- ¶0072), the trenched gate structure 180 including a gate electrode 184 (“gate electrode”- ¶0097), wherein the JFET region 175 extends partially but not completely underneath the trenched gate structure 180, since it is disclosed that structure 240a may extend along only a portion of the bottom surface of gate trench 180 such that JFET region 175 extends underneath the outer edges of gate trench 180, which meets the claim limitation of JFET region extending partially but not completely under trenched gate structure 180 (see ¶0082- “the bottom shielding structure 240a may extend along only a portion of (i.e., may be narrower than) the bottom surface of the gate trench 180, which may increase the available area for conduction 178 at the bottom corners of the gate trench 180 (such that the JFET region 175 may extend underneath the outer edges of the gate trench 180, in addition to along the trench sidewalls”). Regarding claim 16, Figure 2 of Kim discloses wherein the semiconductor layer structure further comprises a trench shielding region 240a (“shielding structures”- ¶0072) having the second conductivity type underneath the trenched gate structure 180. Regarding claim 21, Figure 2 of Kim discloses wherein the JFET region 175 comprises a selectively implanted layer in the semiconductor layer structure (¶0082). Note, regarding the claim limitation “a selectively implanted layer in the semiconductor layer structure” (emphasis added) which is drawn to process steps of a product-by-process claim, such method step(s) are not considered to render an old apparatus patentable where the prior art teaches a product that appears to be the same as, or an obvious variant of, the product set forth in a product-by-process claim although produced by a different process. That is even though product-by-process claims are limited by and defined by the process, the determination of patentability of the claims is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior art product was made by a different process. See MPEP 2113. In this regard, both claimed products and the prior art products would be the same or substantially the same. Allowable Subject Matter Claim 19 is allowed. Regarding independent claim 19, the claim is allowed, because the claim has been rewritten into independent form and includes allowable subject matter as previously indicated in line number 5 of the office action mailed on 6/2/2026. Claims 1, 3-6, 9, 11-13 and 39 would be allowable if rewritten or amended to overcome the objected subject matter set forth in this Office action. Regarding independent claim 1 (which claims 3-6, 9, 11-13 and 39 depend from), the claim has been amended to incorporate the allowable subject of claim 10 as previously indicated in line number 5 of the office action mailed on 6/2/2026. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C CHANG/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Nov 20, 2023
Application Filed
Jun 02, 2026
Non-Final Rejection mailed — §102
Aug 31, 2026
Response Filed
Oct 05, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+13.9%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 686 resolved cases by this examiner. Grant probability derived from career allowance rate.

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