DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on January 4, 2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 29, 2023, June 4, 2024, September 3, 2024 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Device With Protective Ring Structures
Election/Restrictions
Applicant's election with traverse of Device Embodiment 1 (Fig. 6, claims 2, 10, 12-13, and 19) in the reply filed on April 30, 2026 is acknowledged. The traversal is on the ground(s) that the search on the different embodiments may be made without serious burden. This is not found persuasive because as explained in the restriction requirement of April 7, 2026 the embodiments have different structures of connection wires CL1-CL4 and outer gates GSG and would require divergent searches.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-7, 9, 11, and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (US 2019/0131251). Claim 1, Wang discloses (Figs. 2E-2F, 3A) a semiconductor device comprising: a semiconductor substrate (Fig. 3A, 100, semiconductor device comprises semiconductor substrate, Para [0014]) having a first surface (Fig. 3A, 100b, second surface, Para [0015]) and a second surface (Fig. 3A, 100a, first surface, Para [0015]) facing the first surface (100a faces 100b) and including, in a plan view (Figs. 2E-2F), a main chip region (AR, active region, Para [0014]) and a sealing region (PR, peripheral region, Para [0014]) surrounding the main chip region (PR surrounds AR); a front wiring layer (702/704/706, second seal ring structure/metal routing, Para [0024], hereinafter “fwl”) on the first surface of the semiconductor substrate (fwl is on 100b) and including a front wiring structure (fwl includes 704a/704b metal layer and metal routing, Para [0024]); a back wiring layer (302/304/306, first seal ring/metal routing, Para [0033], hereinafter “bwl”) on the second surface of the semiconductor substrate (bwl is on 100a) and including a power wiring structure (304 is considered power wiring as it can conduct electricity being a metal object, Para [0020]); a front ring structure (706, second seal ring structure, Para [0027]) in the front wiring layer of the sealing region (706 is in fwl of PR); and a back ring structure (306, first seal ring structure, Para [0027]) in the back wiring layer of the sealing region (306 is in bwl of PR).
Claim 2, Wang discloses (Figs. 2E-2F, 3A) the semiconductor device of claim 1, wherein the back ring structure (306) is connected to the power wiring structure (306 is connected to 304). Claim 4, Wang discloses (Figs. 2E-2F, 3A) the semiconductor device of claim 1, wherein the front ring structure (706) is connected to the front wiring structure (706 is connected to 704a/704b). Claim 5, Wang discloses (Figs. 2E-2F, 3A) the semiconductor device of claim 1, wherein the front ring structure (706) at least partially overlaps with the back ring structure in a vertical direction (702a/702b of 706 overlaps with 302a/302b of 306 in vertical direction as shown in Fig. 3A). Claim 6, Wang discloses (Figs. 2E-2F, 3A) the semiconductor device of claim 1, wherein each of the front ring structure (706) and the back ring structure (306) has a closed loop shape (706 and 306 are both ring loop patterns, Para [0036]). Claim 7, Wang discloses (Figs. 2E-2F, 3A) the semiconductor device of claim 1, further comprising a power through via (200, TSV, Para [0034]) passing through the semiconductor substrate (200 passes through 100), wherein the power through via is connected to the front wiring structure (200 is connected to 704a/704b through 706 which can be electrically floated, Para [0024]) and the power wiring structure (200 is connected to 304a/304b through 306 which can be electrically floated, Para [0020]). Claim 9, Wang discloses (Figs. 2E-2F, 3A) the semiconductor device of claim 1, wherein the back ring structure (306) includes: a back inner ring structure (306a) surrounding the main chip region (306a surrounds AR); and a back outer ring structure (306b) surrounding the back inner ring structure (306b surrounds 306a), and the back inner ring structure (306a) is separated from the back outer ring structure (306b) in a horizontal direction (306a is separated from 306b in a horizontal direction). Claim 11, Wang discloses (Figs. 2E-2F, 3A) a semiconductor device comprising: a semiconductor substrate (Fig. 3A, 100, semiconductor device comprises semiconductor substrate, Para [0014]) having a first surface (Fig. 3A, 100b, second surface, Para [0015]) and a second surface (Fig. 3A, 100a, first surface, Para [0015]) facing the first surface (100a faces 100b) and including, in a plan view (Figs. 2E-2F), a main chip region (AR, active region, Para [0014]) and a sealing region (PR, peripheral region, Para [0014]) surrounding the main chip region (PR surrounds AR); a front wiring layer (702/704/706, second seal ring structure/metal routing, Para [0024], hereinafter “fwl”) on the first surface of the semiconductor substrate (fwl is on 100b) and including a front wiring structure (fwl includes 704a/704b metal layer and metal routing, Para [0024]); a back wiring layer (302/304/306, first seal ring/metal routing, Para [0033], hereinafter “bwl”) on the second surface of the semiconductor substrate (bwl is on 100a) and including a power wiring structure in the main chip region (304 is considered power wiring as it can conduct electricity being a metal object, Para [0020] and is partially in in AR); a front ring structure (706, second seal ring structure, Para [0027]) in the front wiring layer of the sealing region (706 is in fwl of PR); and a back ring structure (306, first seal ring structure, Para [0027]) in the back wiring layer of the sealing region (306 is in bwl of PR), the front ring structure (706) including, in a plan view (Fig. 2E), a front inner ring structure (706a) surrounding the main chip region (706a surrounds AR) and a front outer ring structure (706b) surrounding the front inner ring structure (706b), and the back ring structure (306) including, in a plan view (although not shown in Fig. 2E, 306 has same structure as 706 and has equivalent portions), a back inner ring structure (306a) surrounding the main chip region (306a would surround AR) and a back outer ring structure (306b) surrounding the back inner ring structure (306b surrounds 306a). Claim 17, Wang discloses (Figs. 2E-2F, 3A) a semiconductor device comprising: a semiconductor substrate (Fig. 3A, 100, semiconductor device comprises semiconductor substrate, Para [0014]) having a first surface (Fig. 3A, 100b, second surface, Para [0015]) and a second surface (Fig. 3A, 100a, first surface, Para [0015]) facing the first surface (100a faces 100b) and including, in a plan view (Figs. 2E-2F), a main chip region (AR, active region, Para [0014]) and a sealing region (PR, peripheral region, Para [0014]) surrounding the main chip region (PR surrounds AR); a front wiring layer (800/702/704/706, passivation layer/second seal ring structure/metal routing, Para [0024], hereinafter “fwl”) on the first surface of the semiconductor substrate (fwl is on 100b) and including a front wiring structure (fwl includes 704a/704b metal layer and metal routing, Para [0024]) in the main chip region (704a/704b are in AR) and a front insulating layer (800) covering the front wiring structure (800 covers 704a/704b); a back wiring layer (300/302/304/306, first interconnection layer/first seal ring/metal routing, Para [0033], hereinafter “bwl”) on the second surface of the semiconductor substrate (bwl is on 100a) and including a power wiring structure in the main chip region (304 is considered power wiring as it can conduct electricity being a metal object, Para [0020] and is partially in in AR) and a back insulating layer (300 may be dielectric material, Para [0019]) covering the power wiring structure (300 covers 304); a power through via (200, TSV, Para [0034]) passing through the semiconductor substrate in a vertical direction (200 passes through 100 in a vertical direction), the power through via being configured to connect the front wiring structure (200 is connected to 704a/704b through 706 which can be electrically floated, Para [0024]) to the power wiring structure (200 is connected to 304a/304b through 306 which can be electrically floated, Para [0020] and so would connect 7041/704b to 304a/304b). a front ring structure (706, second seal ring structure, Para [0027]) in the front wiring layer of the sealing region (706 is in fwl of PR) and including, in a plan view (Fig. 2E), a front inner ring structure (706a) surrounding the main chip region (706a surrounds AR) and a front outer ring structure (706b) surrounding the front inner ring structure (706b surrounds 706a); and a back ring structure (306, first seal ring structure, Para [0027]) in the back wiring layer of the sealing region (306 is in bwl of PR) and including, in a plan view (although not shown in Fig. 2E, 306 has same structure as 706 and has equivalent portions), a back inner ring structure (306a) surrounding the main chip region (306a would surround AR) and a back outer ring structure (306b) surrounding the back inner ring structure (306b surrounds 306a). Claim 18, Wang discloses (Figs. 2E-2F, 3A) the semiconductor device of claim 17, wherein the front inner ring structure (706a) overlaps with the back inner ring structure (306a) in the vertical direction (702a of 706a overlaps 302a of 306a in vertical direction), and the front outer ring structure (706b) overlaps with the back outer ring structure (306b) in the vertical direction (702b of 706b overlaps 302b of 306b in vertical direction).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0131251) as applied to claim 1 above, and further in view of Kitani (US 2007/0044057). Claim 10, Wang discloses (Figs. 2E-2F, 3A) the semiconductor device of claim 1, wherein the back ring structure (306) includes: a back inner ring structure (306a) surrounding the main chip region (306a surrounds AR); and a back outer ring structure (306b) surrounding the back inner ring structure (306b surrounds 306a). Wang does not explicitly disclose the back outer ring structure is connected to the back inner ring structure. However, Kitani (Fig. 11) a back outer ring structure 303b is connected (connected through 312) to a back inner ring structure 303a. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the connection wiring layer of Kitani to the ring structures of Wang as it enhances the conductivity between a power supply and the substrate (Kitani, Para [0050]).
Allowable Subject Matter
Claims 12-13 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Wang (US 2019/0131251), Kitani (US 2007/0044057), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 12 (from which claim 13 depends), Wang discloses (Figs. 2E-2F, 3A) with a back inner ring 306a and power wiring structure 304. Wang does not disclose:
wherein the back inner ring structure is connected to the power wiring structure through the first connection wire.
Regarding Claim 19, Wang discloses (Figs. 2E-2F, 3A) with a back inner ring 306a and power wiring structure 304. Wang does not disclose:
the first connection wire being configured to connect the power wiring structure to the back inner ring structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GUSTAVO G RAMALLO/Examiner, Art Unit 2812
Prosecution Insights