DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I drawn to claims 1-17 in the reply filed on February 20, 2026 is acknowledged. No claims have been amended. No new claims have been added. Claims 18-20 have been withdrawn. Currently claims 1-20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9, 11-14 and 16-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen, Ken-Li et al. (US 20230144120 A1) “Chen et al.”.
Regarding Independent Claim 9, Chen et al. Figs. 2-9 discloses, an apparatus comprising:
a cell contact (“a plurality of plugs 180” ¶ [0031];
a bit-line (“bit line 260” ¶ [0033]); and
an insulating film having an air-gap (“air gap layer 171b,”; “first air gap layer 171b and the second air gap layer 175b are respectively formed the cavities 171a, 175a” ¶ [0034]) between the cell contact and the bit-line (“cavities 171a and 175a are formed between the first spacer 173, the bit lines 260 and the plugs 180, respectively.” ¶ [0033]).
Regarding Claim 11, Chen et al. discloses the limitations of claim 9. Chen et al. Figs. 2-9 further discloses, wherein the insulating film covers both side surface of the bit-line (Figs. 2-9 the insulating film 170 covers both side surface of the bit-line 260).
Regarding Claim 12, Chen et al. discloses the limitations of claim 9. Chen et al. Figs. 2-9 further discloses, wherein the insulating film is a laminated film comprising a plurality of insulating films (“a first material layer 171, a first spacer 173, and a second material 175 are sequentially formed on sidewalls of each bit line 160” ¶ [0031]).
Regarding Claim 13, Chen et al. discloses the limitations of claim 9. Chen et al. Figs. 2-9 further discloses, wherein the cell contact 180 comprises a conductive plug (“a plurality of plugs 180” ¶ [0031]) of which a first side surface (left sides of 180) is covered with a barrier material (“first spacer 173”, ¶ [0031]) and a second side surface (right sides of 180) opposed to the first side surface is coupled to the air-gap (air gap layer 171b, ¶ [0034]) free from the barrier material (the right side 171b is not in contact with the left side 173).
Regarding Claim 14, Chen et al. discloses the limitations of claim 13. Chen et al. Figs. 2-9 further discloses, wherein the conductive plug comprises tungsten (“the plugs 180 for example include a low resistant metal like aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W),” ¶ [0031]).
Regarding Claim 16, Chen et al. discloses the limitations of claim 9. Chen et al. Figs. 1-9 further discloses, wherein said apparatus is a Dynamic Random Access Memory (DRAM) (“The semiconductor memory device 100 of the present embodiment 100 for example includes a dynamic random-access memory (DRAM) device” ¶ [0028]) and the wiring is a bit-line (“bit line 260” ¶ [0033]).
Regarding Claim 17, Chen et al. discloses the limitations of claim 9. Chen et al. Figs. 1-9 further discloses, further comprising a cell capacitor (“a capacitor structure 210” ¶ [0035]); wherein the cell capacitor is electrically connected to the cell contact (“a capacitor structure 210 maybe formed on the substrate 110 to directly contact the storage node pads 181 for electrically connected thereto.” ¶ [0035]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Ken-Li et al. (US 20230144120 A1) “Chen et al.” in view of Park, Kyungwook (US 20210066200 A1) “Park et al.”.
Regarding Independent Claim 1, Chen et al. Figs. 2-9 discloses, an apparatus comprising:
first and second conductive pillars (the spaces which are occupied by plugs 180, evidence here. The term "pillar" will be addressed in the combination rejection below.) in a first layer (the vertical level which is occupied at least in part by plural 180.), each of the first and second conductive pillars (noted spaced occupied by 180) including a conductive plug (“a plurality of plugs 180” ¶ [0031]; Examiner is treating this feature as Applicant has presented, which is to say that a region is labeled "pillar" and then a feature within the pillar region is then introduced as the term "conductive plug".) of which a first side surface (left sides of 180) is covered with a barrier material (“first spacer 173”, ¶ [0031]) and a second side surface (right sides of 180) opposed to the first side surface is coupled to an air-gap (air gap layer 171b, ¶ [0034]) free from the barrier material (the right side 171b is not in contact with the left side 173);
a wiring in the first layer (“bit line 260” ¶ [0033]), the wiring arranged between the first conductive pillar and the second conductive pillar (any single 260 between two 180) such that a first side surface of the wiring faces the barrier material of the first conductive pillar (right side of 260 faces left most 173) and a second side surface opposed to the first side surface of the wiring faces to the air-gap of the second conductive pillar (left side of 260 face right side 171b ).
However, Chen et al. does not explicitly disclose the term "pillar" to describe the feature of 180, but Chen does specify that 180 is a conductive plug.
In the similar field of endeavor of memory devices, Park et al. Figs. 2A-2C discloses a similar feature and refers to it as a "pillar" (“The plurality of conductive plugs may be pillar-shaped” ¶ [0036]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the conductive plug of Chen et al. with the teaching of Park et al. in order to orient the conductive feature like a pillar so as to electrically connect the two regions of the device together, so that they may function in the manner as intended.
Regarding Claim 2, Chen et al. as modified by Park et al. discloses the limitations of claim 1. Chen et al. Figs. 2-9 further discloses, wherein the barrier material 73 of each of the first and second conductive pillars covers all side surfaces of the conductive plug other than the second side surface (the left side 173 does not cover the right side of 180).
Regarding Claim 4, Chen et al. as modified by Park et al. discloses the limitations of claim 1. Chen et al. Figs. 5-9 further discloses, further comprising first and second insulating pillars (“an insulating layer 185 is formed on the plugs 180” ¶ [0034]) in a second layer (the portion above the first layer where the insulating layers 185 is formed) above the first layer;
wherein each of the first and second insulating pillars is at least in part on the air-gap of the corresponding one of the first and second conductive pillars (Figs. 5-9 shows 185 covers the top of air gaps 171a).
Regarding Claim 5, Chen et al. as modified by Park et al. discloses the limitations of claim 1. Chen et al. Figs. 3-9 further discloses, further comprising:
first and second additional conductive pillars in a second layer above the first layer, each of the first and second additional conductive pillars (“a plurality of storage node pads (SN pads) 181 is formed on the plugs 180” ¶ [0032]) being, at least in part, on the barrier material (Figs. 5-9 shows 181 is on 173) of a corresponding one of the first and second conductive pillars 180; and
first and second cell capacitors (“a capacitor structure 210” ¶ [0035]) in a third layer (layer where the capacitor is formed) above the second layer, the first and second cell capacitors coupled respectively to the first and second additional conductive pillars (“a capacitor structure 210 maybe formed on the substrate 110 to directly contact the storage node pads 181 for electrically connected thereto.” ¶ [0035]).
Regarding Claim 6, Chen et al. as modified by Park et al. discloses the limitations of claim 1. Chen et al. Figs. 3-9 further discloses, wherein the conductive plug comprises tungsten (“the plugs 180 for example include a low resistant metal like aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W),” ¶ [0031]).
Regarding Claim 7, Chen et al. as modified by Park et al. discloses the limitations of claim 1. However, Chen et al. does not disclose, wherein the barrier material comprises titanium and titanium nitride.
In the similar field of endeavor of memory devices, Park et al. Figs. 2A-2C discloses, barrier material (“barrier layers 174” ¶ [0039]) comprises titanium and titanium nitride (“barrier layers 174 may be formed of Ti, TiN, or a combination thereof” ¶ [0039]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the barrier layers of Chen et al. with the barrier layers of Park et al. in order to prevent oxygen atoms from diffusing into the outer spacer (Park et al. ¶ [0005-0007]).
Regarding Claim 8, Chen et al. as modified by Park et al. discloses the limitations of claim 1. Chen et al. Figs. 1-9 further discloses, wherein said apparatus is a Dynamic Random Access Memory (DRAM) (“The semiconductor memory device 100 of the present embodiment 100 for example includes a dynamic random-access memory (DRAM) device” ¶ [0028]) and the wiring is a bit-line (“bit line 260” ¶ [0033]).
Regarding Claim 15, Chen et al. discloses the limitations of claim 13. However, Chen et al. does not disclose, wherein the barrier material comprises titanium and titanium nitride.
In the similar field of endeavor of memory devices, Park et al. Figs. 2A-2C discloses, barrier material (“barrier layers 174” ¶ [0039]) comprises titanium and titanium nitride (“barrier layers 174 may be formed of Ti, TiN, or a combination thereof” ¶ [0039]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the barrier layers of Chen et al. with the barrier layers of Park et al. in order to prevent oxygen atoms from diffusing into the outer spacer (Park et al. ¶ [0005-0007]).
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, Ken-Li et al. (US 20230144120 A1) “Chen et al.” in view of Park, Kyungwook (US 20210066200 A1) “Park et al.” further in view of Ikeda, Noriaki (US 20200388618 A1) “Ikeda et al.”.
Regarding Claim 3, Chen et al. as modified by Park et al. discloses the limitations of claim 2. However, Chen et al. does not disclose, wherein the barrier material of each of the first and second conductive pillars further covers a bottom surface of the conductive pillar.
In the similar field of endeavor of memory devices, Ikeda et al. Figs. 2A-2C discloses, barrier material (“barrier layer BR2” ¶ [0017]) of each of the first and second conductive pillars (“conductive structure CS2” ¶ [0017]) further covers a bottom surface of the conductive pillar (“barrier layer BR2 covering a bottom surface and a sidewall of the conductive structure CS2” ¶ [0017]; “In other embodiments, the isolation sidewall IS2 contains an air gap” ¶ [0015]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the barrier layers of Chen et al. with the barrier layers of Ikeda et al. in order to prevent oxygen atoms from diffusing into the outer spacer (Park et al. ¶ [0005-0007]).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, Ken-Li et al. (US 20230144120 A1) “Chen et al.” in view of Park, Kyungwook (US 20210066200 A1) “Park et al.” further in view of KIM, Eun-Jeong (US 20160027727 A1) “KIM et al.”.
Regarding Claim 10, Chen et al. discloses the limitations of claim 9. Chen et al. further discloses, further comprising an additional cell contact arranged (“a plurality of storage node pads (SN pads) 181 is formed on the plugs 180” ¶ [0032]);
wherein the insulating film has no air-gap between the additional cell contact and the bit- line (Figs. 4-9 shows the insulating film 170 has no air-gap between the additional cell contact 181 and the bit- line 260).
However, Chen et al. does not disclose, the bit-line is between the cell contact and the additional cell contact.
In the similar field of endeavor of memory devices, KIM et al. Figs. 2A-2E discloses, the bit-line is between the cell contact and the additional cell contact (“The second plug 117 may be disposed between the neighboring bit lines 115, and neighboring second plugs 117 may be isolated by a plug isolation layer 128” ¶ [0031]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the contact plugs of Chen et al. with the contact plugs of KIM et al. in order to reducing parasitic capacitance between neighboring conductive structures (KIM et al. ¶ [0007]).
Conclusion
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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